rom256x16.xco

含有各类寄存器

# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = F:\Xilinx\OpenHard\HDL_file\test_ROM
SET speedgrade = -6
SET simulationfiles = Behavioral
SET asysymbol = True
SET addpads = False
SET device = xc2s15
SET implementationfiletype = Edif
SET busformat = BusFormatAngleBracketNotRipped
SET foundationsym = False
SET package = cs144
SET createndf = False
SET designentry = VHDL
SET devicefamily = Spartan2
SET formalverification = False
SET removerpms = False
# END Project Options
# BEGIN Select
SELECT Single_Port_Block_Memory family Xilinx,_Inc. 5.0
# END Select
# BEGIN Parameters
CSET handshaking_pins=false
CSET init_value=0
CSET coefficient_file=F:\Xilinx\OpenHard\HDL_file\test_ROM\rom256x16.coe
CSET select_primitive=4kx1
CSET initialization_pin_polarity=Active_High
CSET global_init_value=0
CSET depth=256
CSET write_enable_polarity=Active_High
CSET port_configuration=Read_Only
CSET enable_pin_polarity=Active_High
CSET component_name=rom256x16
CSET active_clock_edge=Rising_Edge_Triggered
CSET additional_output_pipe_stages=0
CSET limit_data_pitch=8
CSET primitive_selection=Optimize_For_Area
CSET enable_pin=true
CSET init_pin=false
CSET write_mode=Read_After_Write
CSET has_limit_data_pitch=false
CSET load_init_file=true
CSET width=16
CSET register_inputs=false
# END Parameters
GENERATE