📄 testrom.vhd
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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity TESTROM is
port (
EN: in STD_LOGIC;
CLK: in STD_LOGIC;
hs : out std_logic;
vs : out std_logic;
r : out std_logic;
g : out std_logic;
b : out std_logic;
--ADDR: in STD_LOGIC_VECTOR (8 downto 0);
DOUT1: out STD_LOGIC_VECTOR (15 downto 0);
DOUT2: out STD_LOGIC_VECTOR (15 downto 0);
LDG : out std_logic
);
end TESTROM;
architecture TESTROM_arch of TESTROM is
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2003 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- The following code must appear in the VHDL architecture header:
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
component rom256x16
port (
addr: IN std_logic_VECTOR(7 downto 0);
clk: IN std_logic;
dout: OUT std_logic_VECTOR(15 downto 0);
en: IN std_logic);
end component;
-- FPGA Express Black Box declaration
attribute fpga_dont_touch: string;
attribute fpga_dont_touch of rom256x16: component is "true";
-- Synplicity black box declaration
attribute syn_black_box : boolean;
attribute syn_black_box of rom256x16: component is true;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.
-- You must compile the wrapper file rom256x16.vhd when simulating
-- the core, rom256x16. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Guide".
component vga_16 is
Port ( clk : in std_logic;
hs : out std_logic;
vs : out std_logic;
r : out std_logic;
g : out std_logic;
b : out std_logic;
innum : in std_logic_vector(15 downto 0);
innum0 : in std_logic_vector(15 downto 0);
innum1 : in std_logic_vector(6 downto 0);
innum2 : in std_logic_vector(6 downto 0);
innum3 : in std_logic_vector(6 downto 0);
innum4 : in std_logic_vector(6 downto 0));
end component;
--signal clk_in : std_logic;
signal count: std_logic_vector(31 downto 0);
signal ADDR: STD_LOGIC_VECTOR (8 downto 0);
signal DO1,DO2: std_logic_vector(15 downto 0);
--signal innum : std_logic_vector(15 downto 0);
--signal innum0 : std_logic_vector(15 downto 0);
signal innum1 : std_logic_vector(6 downto 0);
signal innum2 : std_logic_vector(6 downto 0);
signal innum3 : std_logic_vector(6 downto 0);
signal innum4 : std_logic_vector(6 downto 0);
begin
LDG <= '1';
process(CLK)
begin
if (clk'event and clk='1') then
count<=count+1;
end if;
end process;
--clk_in<=count(22);
addr<=count(31 downto 23);
U1: rom256x16
port map (
addr => addr(7 downto 0),
clk => clk,
en => en,
dout => do1);
dout1<=not do1;
U2: rom256x16
port map (
addr => addr(7 downto 0),
clk => clk,
en => en,
dout => do2);
dout2<=do2;
U3: vga_16 port map(CLK,hs,vs,r,g,b,do1,do2,innum1,innum2,innum3,innum4);
with do1(3 downto 0) SELect innum1<= "1111001" when "0001", --1 "0100100" when "0010", --2 "0110000" when "0011", --3 "0011001" when "0100", --4 "0010010" when "0101", --5 "0000010" when "0110", --6 "1111000" when "0111", --7 "0000000" when "1000", --8 "0010000" when "1001", --9 "0001000" when "1010", --A "0000011" when "1011", --b "1000110" when "1100", --C "0100001" when "1101", --d "0000110" when "1110", --E "0001110" when "1111", --F "1000000" when others; --0
with do1(7 downto 4) SELect innum2<= "1111001" when "0001", --1 "0100100" when "0010", --2 "0110000" when "0011", --3 "0011001" when "0100", --4 "0010010" when "0101", --5 "0000010" when "0110", --6 "1111000" when "0111", --7 "0000000" when "1000", --8 "0010000" when "1001", --9 "0001000" when "1010", --A "0000011" when "1011", --b "1000110" when "1100", --C "0100001" when "1101", --d "0000110" when "1110", --E "0001110" when "1111", --F "1000000" when others; --0
with do1(11 downto 8) SELect innum3<= "1111001" when "0001", --1 "0100100" when "0010", --2 "0110000" when "0011", --3 "0011001" when "0100", --4 "0010010" when "0101", --5 "0000010" when "0110", --6 "1111000" when "0111", --7 "0000000" when "1000", --8 "0010000" when "1001", --9 "0001000" when "1010", --A "0000011" when "1011", --b "1000110" when "1100", --C "0100001" when "1101", --d "0000110" when "1110", --E "0001110" when "1111", --F "1000000" when others; --0
with do1(15 downto 12) SELect innum4<= "1111001" when "0001", --1 "0100100" when "0010", --2 "0110000" when "0011", --3 "0011001" when "0100", --4 "0010010" when "0101", --5 "0000010" when "0110", --6 "1111000" when "0111", --7 "0000000" when "1000", --8 "0010000" when "1001", --9 "0001000" when "1010", --A "0000011" when "1011", --b "1000110" when "1100", --C "0100001" when "1101", --d "0000110" when "1110", --E "0001110" when "1111", --F "1000000" when others; --0
-- synopsys translate_off
Library XilinxCoreLib;
-- synopsys translate_on
-- synopsys translate_off
configuration cfg_TESTROM of TESTROM is
for TESTROM_arch
for all : rom256x16 use entity XilinxCoreLib.C_MEM_SP_BLOCK_V1_0(behavioral)
generic map(
c_has_en => 1,
c_rst_polarity => 1,
c_clk_polarity => 1,
c_width => 16,
c_has_do => 1,
c_has_di => 0,
c_en_polarity => 1,
c_has_we => 0,
c_has_rst => 0,
c_address_width => 8,
c_read_mif => 1,
c_depth => 256,
c_pipe_stages => 0,
c_mem_init_radix => 16,
c_default_data => "1",
c_mem_init_file => "C:\Xilinx\active\projects\TESTRAM\rom256x16.mif",
c_we_polarity => 1,
c_generate_mif => 1);
end for;
end for;
end cfg_TESTROM;
-- synopsys translate_on
end TESTROM_arch;⌨️ 快捷键说明
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