4选1.vhd

含有各类寄存器

entity MUX4_1 is
       port (   I : in bit_vector(3 downto 0);         -- data input
                     S   : in bit_vector(1 downto 0);         -- select input
                     E_N    : in bit;                       -- enable input low active
                     Y, Y_N: out bit);                       -- outputs
end MUX4_1;
architecture  MUX_PRO of MUX4_1 is
begin
MUX:   process   (I, S, E_N)
       variable TEMP: bit_vector(2 downto 0);   -- only allowed in processes
       begin
           TEMP := E_N & S;          --variable assignment, concatenation of two bits
           case TEMP is               -- control expression: prefer signals or variables
              when "000" => Y <= I(0); Y_N <= not I(0);
              when "001" => Y <= I(1); Y_N <= not I(1);
              when "010" => Y <= I(2); Y_N <= not I(2);
              when "011" => Y <= I(3); Y_N <= not I(3);
              when others   => Y <=  '0';   Y_N <=  '1';
           end case;
         end process MUX;
end MUX_PRO;