testram.vhd

含有各类寄存器

--In this example, a 512K x 4 RAM (Port A) and a 128 x 16
--RAM (Port B) are created out of a single Block Selec-tRAM+.
--The address space for the RAM is split by fixing the
--MSB of Port A to 1 (V CC ) for the upper 2K bits and the MSB
--of Port B to 0 (GND) for the lower 2K bits.
--Block Memory Generation
--The CoreGen program generates memory structures using
--the Block SelectRAM+ features. This program outputs
--VHDL or Verilog simulation code templates and an EDIF
--file for inclusion in a design.
--VHDL Initialization Example

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_UNSIGNED.all;

entity testram is
  port (
        CLKIN, WE: in STD_LOGIC;
	   hs,vs, r,g,b: out std_logic;
--        ADDR: in STD_LOGIC_VECTOR (8 downto 0);
--        DIN: in STD_LOGIC_VECTOR (7 downto 0);
        DOUT: out STD_LOGIC_VECTOR (7 downto 0);
        CLKOUT: out std_logic;
		  LDG : out std_logic
    );
end testram;

architecture testram_arch of testram is
 
signal logic0, logic1: std_logic;
signal CLK: std_logic;
signal Q: std_logic_vector(31 downto 0);
signal ADDR: std_logic_vector(8 downto 0);
signal DIN: std_logic_vector(7 downto 0);
signal DO: std_logic_vector(7 downto 0);
signal innum,innum0: std_logic_vector(15 downto 0);
signal innum1,innum2,innum3,innum4: std_logic_vector( 6 downto 0);

component vga_16
	 Port ( clk : in std_logic;
           hs : out std_logic;
           vs : out std_logic;
           r : out std_logic;
           g : out std_logic;
           b : out std_logic;
		 	  innum  : in std_logic_vector(15 downto 0);
			  innum0 : in std_logic_vector(15 downto 0); 
           innum1 : in std_logic_vector(6 downto 0);
           innum2 : in std_logic_vector(6 downto 0);
           innum3 : in std_logic_vector(6 downto 0);
		     innum4 : in std_logic_vector(6 downto 0));
end component;

component RAMB4_S8
--synopsys translate_off
generic( INIT_00,INIT_01, INIT_02, INIT_03, INIT_04, INIT_05, INIT_06, INIT_07,
INIT_08, INIT_09, INIT_0a, INIT_0b, INIT_0c, INIT_0d, INIT_0e, INIT_0f : BIT_VECTOR(255
downto 0)
:= X"0000000000000000000000000000000000000000000000000000000000000000");
--synopsys translate_on
port (WE, EN, RST, CLK: in STD_LOGIC;
		ADDR: in STD_LOGIC_VECTOR(8 downto 0);
		DI: in STD_LOGIC_VECTOR(7 downto 0);
		DO: out STD_LOGIC_VECTOR(7 downto 0));
end component;
--synopsys dc_script_begin
--set_attribute ram0 INIT_00
--"0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF" -type string
--set_attribute ram0 INIT_01
--"FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210" -type string
--synopsys dc_script_end

begin

LDG <= '1';
logic0 <= '0';
logic1 <= '1';
U0: vga_16 port map(clkin, hs, vs, r,g,b,innum,innum0,innum1,innum2,innum3,innum4);

innum0<="00000000"& DO;
innum<="0000000"& addr;

process(CLKIN)
BEGIN
IF (CLKIN'EVENT AND CLKIN='1') THEN
  Q <= Q + 1 ;
END IF;  
END PROCESS;
CLKOUT <= Q(22);
CLK <= Q(22);
ADDR <= Q(31 DOWNTO 23);
DIN <= Q(31 DOWNTO 24);

ram0: RAMB4_S8
--synopsys translate_off
generic map (
INIT_00 => X"0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF",
INIT_01 => X"FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210")
--synopsys translate_on
port map (WE=>WE, EN=>logic1, RST=>logic0, CLK=>CLKIN,ADDR=>ADDR, DI=>DIN, DO=>DO);
 DOUT<= DO;				--not DO;
		 
  
 
--HEX-to-seven-segment decoder
--   HEX:   in    STD_LOGIC_VECTOR (3 downto 0);
--   LED:   out   STD_LOGIC_VECTOR (6 downto 0);
-- 
-- segment encoding
--      0
--     ---  
--  5 |   | 1
--     ---   <- 6
--  4 |   | 2
--     ---
--      3
   
    with DO(7 downto 4) SELect
   innum4<= "1111001" when "0001",   --1
         "0100100" when "0010",   --2
         "0110000" when "0011",   --3
         "0011001" when "0100",   --4
         "0010010" when "0101",   --5
         "0000010" when "0110",   --6
         "1111000" when "0111",   --7
         "0000000" when "1000",   --8
         "0010000" when "1001",   --9
         "0001000" when "1010",   --A
         "0000011" when "1011",   --b
         "1000110" when "1100",   --C
         "0100001" when "1101",   --d
         "0000110" when "1110",   --E
         "0001110" when "1111",   --F
         "1000000" when others;   --0
 	 with DO(3 downto 0) SELect
   innum3<= "1111001" when "0001",   --1
         "0100100" when "0010",   --2
         "0110000" when "0011",   --3
         "0011001" when "0100",   --4
         "0010010" when "0101",   --5
         "0000010" when "0110",   --6
         "1111000" when "0111",   --7
         "0000000" when "1000",   --8
         "0010000" when "1001",   --9
         "0001000" when "1010",   --A
         "0000011" when "1011",   --b
         "1000110" when "1100",   --C
         "0100001" when "1101",   --d
         "0000110" when "1110",   --E
         "0001110" when "1111",   --F
         "1000000" when others;   --0
	 with DO(7 downto 4) SELect
   innum2<= "1111001" when "0001",   --1
         "0100100" when "0010",   --2
         "0110000" when "0011",   --3
         "0011001" when "0100",   --4
         "0010010" when "0101",   --5
         "0000010" when "0110",   --6
         "1111000" when "0111",   --7
         "0000000" when "1000",   --8
         "0010000" when "1001",   --9
         "0001000" when "1010",   --A
         "0000011" when "1011",   --b
         "1000110" when "1100",   --C
         "0100001" when "1101",   --d
         "0000110" when "1110",   --E
         "0001110" when "1111",   --F
         "1000000" when others;   --0
	 with DO(3 downto 0) SELect
   innum1<= "1111001" when "0001",   --1
         "0100100" when "0010",   --2
         "0110000" when "0011",   --3
         "0011001" when "0100",   --4
         "0010010" when "0101",   --5
         "0000010" when "0110",   --6
         "1111000" when "0111",   --7
         "0000000" when "1000",   --8
         "0010000" when "1001",   --9
         "0001000" when "1010",   --A
         "0000011" when "1011",   --b
         "1000110" when "1100",   --C
         "0100001" when "1101",   --d
         "0000110" when "1110",   --E
         "0001110" when "1111",   --F
         "1000000" when others;   --0

end testram_arch;