📄 jgcj_top.vhd
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity JGCJ_top is
Port(RST : in std_logic;
CLKIN : in std_logic;
CLKOUT: out std_logic;
ad_in : in std_logic_vector(4 downto 0);
din: in std_logic_vector(10 downto 0);
data_IO : inout std_logic_vector(15 downto 0);
SIO : inout std_logic_vector(2 downto 0);
SIG : in std_logic;
test_ctrl: in std_logic;
ad_gate_O: out std_logic;
delay_ctrl: in std_logic;
delay_clkO: out std_logic;
dist: out std_logic_vector(15 downto 0);
target_out: out std_logic_vector(4 downto 0);
trig_out: out std_logic;
gate_out: out std_logic;
LED1 : out std_logic_vector(6 downto 0);
LED2 : out std_logic_vector(6 downto 0);
LED3 : out std_logic_vector(6 downto 0);
LED4 : out std_logic_vector(6 downto 0);
LED5 : out std_logic_vector(6 downto 0);
LED_ctl : out std_logic_vector(2 downto 0));
end JGCJ_top;
architecture Behavioral of JGCJ_top is
--Virtex CLKDLL instantiation--See XAPP 132 for more examples--Use "CLK" as your internal clock signal -- CLKIN_P, RST : in std_logic;-- LOCKED : out std_logic --**Insert the following between the 'architecture' and---'begin' keywords** component CLKDLL port (CLKIN, CLKFB, RST : in STD_LOGIC; CLK0, CLK90, CLK180, CLK270, CLK2X, CLKDV, LOCKED : out std_logic);end component; component IBUFG port (I : in STD_LOGIC; O : out std_logic);end component; component BUFG port (I : in STD_LOGIC; O : out std_logic);end component;----- Component SRL16 -----component SRL16-- generic ( INIT : bit_vector := X"0000");-- port (D : in STD_logic; CLK : in STD_logic; A0 : in STD_logic; A1 : in STD_logic; A2 : in STD_logic; A3 : in STD_logic; Q : out STD_logic); end component;----- Component RAMB4_S16 -----
component RAMB4_S16
--
generic (INIT_00,INIT_01,INIT_02,INIT_03,INIT_04,INIT_05,INIT_06,INIT_07,INIT_08,INIT_09,INIT_0a,INIT_0b,INIT_0c,INIT_0d,INIT_0e,INIT_0f :
bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000");
--
port (DI : in STD_LOGIC_VECTOR (15 downto 0);
EN : in STD_logic;
WE : in STD_logic;
RST : in STD_logic;
CLK : in STD_logic;
ADDR : in STD_LOGIC_VECTOR (7 downto 0);
DO : out STD_LOGIC_VECTOR (15 downto 0));
end component;
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
component sum
port (
B: IN std_logic_VECTOR(15 downto 0);
Q: OUT std_logic_VECTOR(15 downto 0);
CLK: IN std_logic;
C_IN: IN std_logic;
CE: IN std_logic;
ACLR: IN std_logic);
end component;
-- FPGA Express Black Box declaration
attribute fpga_dont_touch: string;
attribute fpga_dont_touch of sum: component is "true";
-- Synplicity black box declaration
attribute syn_black_box : boolean;
attribute syn_black_box of sum: component is true;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
component bcd_rom
port (
addr: IN std_logic_VECTOR(7 downto 0);
clk: IN std_logic;
dout: OUT std_logic_VECTOR(15 downto 0);
en: IN std_logic);
end component;
-- FPGA Express Black Box declaration
--attribute fpga_dont_touch: string;
--attribute fpga_dont_touch of bcd_rom: component is "true";
-- Synplicity black box declaration
--attribute syn_black_box : boolean;
--attribute syn_black_box of bcd_rom: component is true;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
signal target_DM,target_DL: std_logic_vector(10 downto 0);
signal trig, gate : std_logic;
signal N : std_logic_vector(17 downto 0);
signal delay_clk : std_logic;
signal delay_cnt: std_logic_vector(17 downto 0);
signal target_dist: std_logic_vector(15 downto 0);
signal dist_sum: std_logic_vector(15 downto 0);
signal bcd_out: std_logic_vector(15 downto 0);
signal BRAM_in, BRAM_out: std_logic_vector(15 downto 0);
signal BRAM_addr: std_logic_vector(7 downto 0);
signal bcd_addr: std_logic_vector(7 downto 0);
signal ad_gate: std_logic;
signal target: std_logic_vector(4 downto 0);
signal logic1, logic0 : std_logic;
signal CLK_IN, CLK, CLK0, CLK_2X, RESET,CLK2X, locked: std_logic;
signal CLK_0, CLK_X, CLK4X, CLK_4X, locked2: std_logic;
signal MX : std_logic_vector(4 downto 0);
signal gate_L,gate_M : std_logic_vector(15 downto 0);
begin
logic1<='1';
logic0<=not rst;
--**Insert the following after the 'begin' keyword**U1: IBUFG port map (I=>CLKIN, O=>CLK_IN); U2: CLKDLL port map (CLKIN=>CLK_IN, CLKFB=>CLK2X, RST=>logic0, CLK2X=>CLK_2X, LOCKED=>LOCKED); U3: BUFG port map (I=>CLK4X, O=>CLK);
U4: BUFG port map (I=>CLK_2X, O=>CLK2X);
U5: CLKDLL port map (CLKIN=>CLK2X, CLKFB=>CLK, RST=>not RESET,CLK2X=>CLK4X, LOCKED=>LOCKED2);
U9: SRL16 port map (LOCKED,CLK2X,logic1,logic1,logic1,logic1,reset);
U6:RAMB4_S16 port map(target_dist,logic1,logic1,logic0,clk,BRAM_addr,BRAM_out);
clkout<=CLK;
--dist<=target_dist(15 downto 0);
dist<=not BRAM_out;
process(rst,clk)
begin
if rst='0' then
N<=(others=>'0');
delay_clk<='0';
elsif clk'event and clk='1' then
N<=N+1;
if N=100000 then
delay_clk<='1';
-- elsif N=100000 then
-- delay_clk<='0';
-- elsif N=150000 then
-- delay_clk<='1';
elsif N=200000 then
delay_clk<='0';
N<=(others=>'0');
end if;
end if;
end process;
delay_clkO<=delay_clk;
data_IO<=not ('0' & dist_sum(15 downto 1));
process (rst,clk)
begin
if rst='0' then
trig<='0';
elsif clk'event and clk='1' then
if N<10 then
trig<='1';
else
trig <='0';
end if;
end if;
end process;
trig_out<=trig;
process(delay_clk,rst)
begin
if rst='0' then
delay_cnt<=(others=>'0');
elsif delay_clk'event and delay_clk='1' then
if delay_ctrl='1' then
delay_cnt<=delay_cnt+1;
else delay_cnt<=delay_cnt;
end if;
end if;
end process;
process (rst,clk)
begin
if rst='0' then
gate<='0';
elsif clk'event and clk='1' then
if N=gate_M then
gate<='1';
elsif N=gate_L then
gate <='0';
end if;
end if;
end process;
process(rst,clk)
begin
if rst='0' then
ad_gate<='0';
elsif clk'event and clk='1' then
if N=target_DM then
ad_gate<='1';
elsif N=target_DL then
ad_gate<='0';
end if;
end if;
end process;
ad_gate_O<=ad_gate;
process(clk,rst)
begin
if rst='0' then
target<=(others=>'0');
elsif clk'event and clk='1' then
if ad_gate='1' then
target<=ad_in;
else target<=(others=>'0');
end if;
end if;
end process;
target_out<=not target;
process(rst,clk)
begin
if rst='0' then
target_dist<=(others=>'0');
elsif clk'event and clk='1' then
if target>MX then
target_dist<=N(15 downto 0);
end if;
end if;
end process;
process(rst,clk)
begin
if rst='0' then
BRAM_addr<=(others=>'0');
elsif delay_clk'event and delay_clk='1' then
if test_ctrl='0' and BRAM_addr< 256 then
BRAM_addr<=BRAM_addr+1;
end if;
end if;
end process;
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
U7 : sum
port map (
B => BRAM_out,
Q => dist_sum,
CLK => CLK,
C_IN => logic0,
CE =>not test_ctrl,
ACLR =>not rst);
-- INST_TAG_END ------ End INSTANTIATION Template ------------
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
U8 : bcd_rom
port map (
addr => bcd_addr,
clk => clk,
dout => bcd_out,
en => logic1);
-- INST_TAG_END ------ End INSTANTIATION Template ------------
LED4<=bcd_out(14 downto 8);
LED3<=bcd_out(6 downto 0);
process(rst,clk, dist_sum)
begin
if rst='0' then
bcd_addr<=(others=>'0');
elsif clk'event and clk='1' then
case dist_sum(10 downto 9) is
when "00" => bcd_addr<=dist_sum(8 downto 1);
when "01" => bcd_addr<=dist_sum(8 downto 1)+56;
when "10" => bcd_addr<=dist_sum(8 downto 1)+12;
when "11" => bcd_addr<=dist_sum(8 downto 1)+76;
when others => null;
end case;
end if;
end process;
process(clk, rst, dist_sum)
begin
if rst='0' then
LED5<="1000000";
elsif clk'event and clk='1' then
if test_ctrl='0' then
case dist_sum(10 downto 9) is
when "00" =>
if dist_sum(8 downto 0)>"00000000" and dist_sum(8 downto 0)<"01100100" then LED5<="1000000";
elsif dist_sum(8 downto 1)>"01100100" and dist_sum(8 downto 1)<"11001000" then LED5<="1111001";
elsif dist_sum(8 downto 1)>"11001000" then LED5<="0100100";
-- elsif dist_sum(8 downto 1)="00000000" then LED5<="1000000";
end if;
when "01" =>
if dist_sum(8 downto 1)>"00101100" and dist_sum(8 downto 1)<"10010000" then LED5<="0110000";
elsif dist_sum(8 downto 1)>"10010000" and dist_sum(8 downto 1)<"11110100" then LED5<="0011001";
elsif dist_sum(8 downto 1)>"11110100" then LED5<="0010010";
-- elsif dist_sum(8 downto 1)="00000000" then LED5<="0100100";
end if;
when "10" =>
if dist_sum(8 downto 1)>"01011000" and dist_sum(8 downto 1)<"10111100" then LED5<="0000010";
elsif dist_sum(8 downto 1)>"10111100" then LED5<="1111000";
-- elsif dist_sum(8 downto 1)="00000000" then LED5<="0010010";
end if;
when "11" =>
if dist_sum(8 downto 1)>"00100000" and dist_sum(8 downto 1)<"10000100" then LED5<="0000000";
elsif dist_sum(8 downto 1)>"10000100" and dist_sum(8 downto 1)<"11101000" then LED5<="0010000";
elsif dist_sum(8 downto 1)>"11101000" and dist_sum(8 downto 0)<"11111111" then LED5<="1000000";
end if;
when others => null;
end case;
end if;
end if;
end process;
process(rst,clk)
begin
if rst='0' then
MX<=(others=>'0');
gate_L<=(others=>'0');
gate_M<=(others=>'0');
target_DM<=(others=>'0');
target_DL<=(others=>'0');
elsif clk'event and clk='1' then
case SIO is --state
when "000" => --Normal
MX<="01110";
target_DM<="00010000000";
target_DL<="00010001010";
when "001" => --Ignore
gate_M<= "00"&BRAM_out(15 downto 2);
gate_L<= BRAM_out(13 downto 0) & "00";
when "010" => --Complex
gate_M<= "00"&BRAM_out(15 downto 2);
gate_L<= BRAM_out(13 downto 0) & "00";
when "011" => --Scan
gate_M<= "00"&BRAM_out(15 downto 2);
gate_L<= BRAM_out(13 downto 0) & "00";
target_DM<=din + BRAM_addr;
target_DL<=din + BRAM_addr + 10;
when "100" => --Rain
MX<="00111";
when others =>
null;
end case;
end if;
end process;
gate_out<=gate;
with BRAM_addr(7 downto 4) SELect
LED2<= "1111001" when "0001", --1
"0100100" when "0010", --2
"0110000" when "0011", --3
"0011001" when "0100", --4
"0010010" when "0101", --5
"0000010" when "0110", --6
"1111000" when "0111", --7
"0000000" when "1000", --8
"0010000" when "1001", --9
"0001000" when "1010", --A
"0000011" when "1011", --b
"1000110" when "1100", --C
"0100001" when "1101", --d
"0000110" when "1110", --E
"0001110" when "1111", --F
"1000000" when others; --0
with BRAM_addr(3 downto 0) SELect
LED1<= "1111001" when "0001", --1
"0100100" when "0010", --2
"0110000" when "0011", --3
"0011001" when "0100", --4
"0010010" when "0101", --5
"0000010" when "0110", --6
"1111000" when "0111", --7
"0000000" when "1000", --8
"0010000" when "1001", --9
"0001000" when "1010", --A
"0000011" when "1011", --b
"1000110" when "1100", --C
"0100001" when "1101", --d
"0000110" when "1110", --E
"0001110" when "1111", --F
"1000000" when others; --0
end Behavioral;
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