fpswap.vhd

来自「一个32位元的浮点数加法器」· VHDL 代码 · 共 36 行

--modified 2007,03 v1
--modified 2007,04,09 v2
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY FPswap IS
   GENERIC( 
      width : integer := 29
   );
   PORT( 
      A_in    : IN     std_logic_vector (width-1 DOWNTO 0);
      B_in    : IN     std_logic_vector (width-1 DOWNTO 0);
      swap_AB : IN     std_logic;
      A_out   : OUT    std_logic_vector (width-1 DOWNTO 0);
      B_out   : OUT    std_logic_vector (width-1 DOWNTO 0)
   );
END FPswap ;

ARCHITECTURE FPswap OF FPswap IS
BEGIN

PROCESS(A_in, B_in, swap_AB)
BEGIN
   IF (swap_AB='1') THEN
      A_out <= B_in;
      B_out <= A_in;
   ELSE
      A_out <= A_in;
      B_out <= B_in;
   END IF;
END PROCESS;

END FPswap;