📄 des_cal.v
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/* case({k1_sel_key1,Left_first})
2'b11:k1_reg<={k1_reg[28:55],buffin[31:25],buffin[23:17],buffin[15:9],buffin[7:1]};
2'b10:k1_reg<={buffin[31:25],buffin[23:17],buffin[15:9],buffin[7:1],k1_reg[0:27]};
default: k1_reg<=k1_reg;
endcase */
end
end
//------------------------------------------------------------------
// k2_reg
//------------------------------------------------------------------
always @ (posedge clk or negedge rst_n)
begin
if(!rst_n) k2_reg<=56'd0;
else if(sw_rst) k2_reg<=56'd0;
else
begin
if(k2_sel_key2) k2_reg<={buffin[31:25],buffin[23:17],buffin[15:9],buffin[7:1],k2_reg[0:27]};
/*case({k2_sel_key2,Left_first})
2'b11:k2_reg<={k2_reg[28:55],buffin[31:25],buffin[23:17],buffin[15:9],buffin[7:1]};
2'b10:k2_reg<={buffin[31:25],buffin[23:17],buffin[15:9],buffin[7:1],k2_reg[0:27]};
default: k2_reg<=k2_reg;
endcase */
end
end
//------------------------------------------------------------------
// k3_reg
//------------------------------------------------------------------
always @ (posedge clk or negedge rst_n)
begin
if(!rst_n) k3_reg<=56'd0;
else if(sw_rst) k3_reg<=56'd0;
else
begin
if(k3_sel_key3) k3_reg<={buffin[31:25],buffin[23:17],buffin[15:9],buffin[7:1],k3_reg[0:27]};
/* case({k3_sel_key3,Left_first})
2'b11:k3_reg<={k3_reg[28:55],buffin[31:25],buffin[23:17],buffin[15:9],buffin[7:1]};
2'b10:k3_reg<={buffin[31:25],buffin[23:17],buffin[15:9],buffin[7:1],k3_reg[0:27]};
default:k3_reg<=k3_reg;
endcase */
end
end
//------------------------------------------------------------------
// iv_reg
//------------------------------------------------------------------
/*
wire iv_load_lst,iv_load_hst;
assign iv_load_lst=iv_load & Left_first;
assign iv_load_hst=iv_load & (!Left_first); */
always @ (posedge clk or negedge rst_n)
begin
if(!rst_n) iv_reg<=64'h1234567890abcdef;
else if(sw_rst) iv_reg<=64'h1234567890abcdef;
else
begin
case({iv_sel_data,iv_sel_tmp,iv_shift_1,iv_shift_8,iv_shift_16,iv_shift_32,iv_shift_64,iv_load,iv_back_tmp})
9'b100000000,9'b000000100: iv_reg<=data_reg;
9'b010000000,9'b000000101: iv_reg<=tmp_reg;
9'b001000000: iv_reg<={iv_reg[1:63],data_reg[0]};
9'b000100000: iv_reg<={iv_reg[8:63],data_reg[0:7]};
9'b000010000: iv_reg<={iv_reg[16:63],data_reg[0:15]};
9'b000001000: iv_reg<={iv_reg[32:63],data_reg[0:31]};
//10'b0000000100: iv_reg<={iv_reg[32:63],buffin[31:0]};
9'b000000010: iv_reg<={buffin[31:0],iv_reg[0:31]};
9'b001000001: iv_reg<={iv_reg[1:63],tmp_reg[0]};
9'b000100001:iv_reg<={iv_reg[8:63],tmp_reg[0:7]};
9'b000010001:iv_reg<={iv_reg[16:63],tmp_reg[0:15]};
9'b000001001:iv_reg<={iv_reg[32:63],tmp_reg[0:31]};
default:iv_reg<=iv_reg;
endcase
/* case({iv_sel_data,iv_sel_tmp,iv_shift_1,iv_shift_8,iv_shift_16,iv_shift_32,iv_shift_64,iv_load_lst,iv_load_hst,iv_back_tmp})
10'b1000000000,10'b0000001000: iv_reg<=data_reg;
10'b0100000000,10'b0000001001: iv_reg<=tmp_reg;
10'b0010000000: iv_reg<={iv_reg[1:63],data_reg[0]};
10'b0001000000: iv_reg<={iv_reg[8:63],data_reg[0:7]};
10'b0000100000: iv_reg<={iv_reg[16:63],data_reg[0:15]};
10'b0000010000: iv_reg<={iv_reg[32:63],data_reg[0:31]};
//10'b0000000100: iv_reg<={iv_reg[32:63],buffin[31:0]};
10'b0000000010: iv_reg<={buffin[31:0],iv_reg[0:31]};
10'b0010000001: iv_reg<={iv_reg[1:63],tmp_reg[0]};
10'b0001000001:iv_reg<={iv_reg[8:63],tmp_reg[0:7]};
10'b0000100001:iv_reg<={iv_reg[16:63],tmp_reg[0:15]};
10'b0000010001:iv_reg<={iv_reg[32:63],tmp_reg[0:31]};
default:iv_reg<=iv_reg;
endcase */
end
end
//------------------------------------------------------------------
// data_reg
//------------------------------------------------------------------
wire [0:63] data_x1,data_x2;
assign data_x1=(buff_xor_iv)? buff_reg:
(data_xor_iv)? data_reg:
(tmp_xor_data_1)?{tmp_reg[0],63'd0}:
(tmp_xor_data_8)? {tmp_reg[0:7],56'd0}:
(tmp_xor_data_16)? {tmp_reg[0:15],48'd0}:
(tmp_xor_data_32)? {tmp_reg[0:31],32'd0}:
(tmp_xor_data_64)?tmp_reg:64'd0;
assign data_x2=(buff_xor_iv||data_xor_iv)? iv_reg:
(tmp_xor_data_1)?{data_reg[0],63'd0}:
(tmp_xor_data_8)? {data_reg[0:7],56'd0}:
(tmp_xor_data_16)? {data_reg[0:15],48'd0}:
(tmp_xor_data_32) ? {data_reg[0:31],32'd0}:
(tmp_xor_data_64)? data_reg:64'd0;
wire data_xor=buff_xor_iv || data_xor_iv ||tmp_xor_data_1|| tmp_xor_data_8 ||tmp_xor_data_16 || tmp_xor_data_32 || tmp_xor_data_64;
always @ (posedge clk or negedge rst_n)
begin
if(!rst_n) data_reg<=64'd0;
else if(sw_rst) data_reg<=64'd0;
else
begin
case({IP,IP_1,data_sel_buff,data_sel_com1,data_sel_com2,data_sel_iv,data_xor})
7'b1000000:data_reg<={data_reg[57],data_reg[49],data_reg[41],data_reg[33],data_reg[25],data_reg[17],data_reg[9],data_reg[1],
data_reg[59],data_reg[51],data_reg[43],data_reg[35],data_reg[27],data_reg[19],data_reg[11],data_reg[3],
data_reg[61],data_reg[53],data_reg[45],data_reg[37],data_reg[29],data_reg[21],data_reg[13],data_reg[5],
data_reg[63],data_reg[55],data_reg[47],data_reg[39],data_reg[31],data_reg[23],data_reg[15],data_reg[7],
data_reg[56],data_reg[48],data_reg[40],data_reg[32],data_reg[24],data_reg[16],data_reg[8],data_reg[0],
data_reg[58],data_reg[50],data_reg[42],data_reg[34],data_reg[26],data_reg[18],data_reg[10],data_reg[2],
data_reg[60],data_reg[52],data_reg[44],data_reg[36],data_reg[28],data_reg[20],data_reg[12],data_reg[4],
data_reg[62],data_reg[54],data_reg[46],data_reg[38],data_reg[30],data_reg[22],data_reg[14],data_reg[6]};
7'b0100000:data_reg<={data_reg[39],data_reg[7],data_reg[47],data_reg[15],data_reg[55],data_reg[23],data_reg[63],data_reg[31],
data_reg[38],data_reg[6],data_reg[46],data_reg[14],data_reg[54],data_reg[22],data_reg[62],data_reg[30],
data_reg[37],data_reg[5],data_reg[45],data_reg[13],data_reg[53],data_reg[21],data_reg[61],data_reg[29],
data_reg[36],data_reg[4],data_reg[44],data_reg[12],data_reg[52],data_reg[20],data_reg[60],data_reg[28],
data_reg[35],data_reg[3],data_reg[43],data_reg[11],data_reg[51],data_reg[19],data_reg[59],data_reg[27],
data_reg[34],data_reg[2],data_reg[42],data_reg[10],data_reg[50],data_reg[18],data_reg[58],data_reg[26],
data_reg[33],data_reg[1],data_reg[41],data_reg[9],data_reg[49],data_reg[17],data_reg[57],data_reg[25],
data_reg[32],data_reg[0],data_reg[40],data_reg[8],data_reg[48],data_reg[16],data_reg[56],data_reg[24]};
7'b0010000: //data_sel_buff
data_reg<=buff_reg;
7'b0001000: //data_sel_com1
data_reg<={data_reg[32:63],r2};
7'b0000100://data_sel_com2
data_reg<={r2,data_reg[32:63]};
7'b0000010://data_sel_iv
data_reg<=iv_reg;
7'b0000001://data_xor
data_reg<=data_x1^data_x2;
default: data_reg<=data_reg;
endcase
end
end
always @ (r1[0:5])
begin
//case(r1[5:0]) //s1
case({r1[0],r1[5],r1[1],r1[2],r1[3],r1[4]}) //s1
6'b00_1110,6'b01_0000,6'b10_1111,6'b11_1101,
6'b00_0100,6'b01_0101,6'b10_0110,6'b11_0011,
6'b00_0001,6'b01_0011,6'b10_0000,6'b11_0100,
6'b00_1010,6'b01_1001,6'b10_0101,6'b11_1110,
6'b00_0111,6'b01_1111,6'b10_0011,6'b11_0010,
6'b00_1001,6'b01_1000,6'b10_1101,6'b11_1100,
6'b00_1011,6'b01_1010,6'b10_1001,6'b11_0001,
6'b00_0000,6'b01_0100,6'b10_0010,6'b11_1011:s10=1'b0;
default: s10=1'b1;
endcase
case({r1[0],r1[5],r1[1],r1[2],r1[3],r1[4]})
6'b00_1110,6'b01_0000,6'b10_1111,6'b11_1101,
6'b00_0011,6'b01_0111,6'b10_0001,6'b11_0110,
6'b00_0001,6'b01_0011,6'b10_0000,6'b11_0100,
6'b00_1100,6'b01_1101,6'b10_1110,6'b11_1000,
6'b00_0111,6'b01_1111,6'b10_0011,6'b11_0010,
6'b00_1101,6'b01_1100,6'b10_1010,6'b11_0101,
6'b00_1011,6'b01_1010,6'b10_1001,6'b11_0001,
6'b00_0010,6'b01_0110,6'b10_0100,6'b11_1111:s11=1'b0;
default: s11=1'b1;
endcase
case({r1[0],r1[5],r1[1],r1[2],r1[3],r1[4]})
6'b00_1110,6'b01_0000,6'b10_1111,6'b11_1101,
6'b00_0011,6'b01_0111,6'b10_0001,6'b11_0110,
6'b00_0100,6'b01_0101,6'b10_0110,6'b11_0011,
6'b00_1000,6'b01_1110,6'b10_1100,6'b11_1010,
6'b00_0111,6'b01_1111,6'b10_0011,6'b11_0010,
6'b00_1101,6'b01_1100,6'b10_1010,6'b11_0101,
6'b00_1001,6'b01_1000,6'b10_1101,6'b11_1100,
6'b00_0110,6'b01_1011,6'b10_0111,6'b11_1001:s12=1'b0;
default: s12=1'b1;
endcase
case({r1[0],r1[5],r1[1],r1[2],r1[3],r1[4]})
6'b00_1110,6'b01_0000,6'b10_1111,6'b11_1101,
6'b00_0011,6'b01_0111,6'b10_0001,6'b11_0110,
6'b00_0100,6'b01_0101,6'b10_0110,6'b11_0011,
6'b00_1000,6'b01_1110,6'b10_1100,6'b11_1010,
6'b00_0001,6'b01_0011,6'b10_0000,6'b11_0100,
6'b00_1100,6'b01_1101,6'b10_1110,6'b11_1000,
6'b00_1010,6'b01_1001,6'b10_0101,6'b11_1110,
6'b00_1111,6'b01_0010,6'b10_1011,6'b11_0111:s13=1'b0;
default: begin
/* s10=1'b1; s11=1'b1;*/ s13=1'b1;
end
endcase
end
always @(r1[6:11])
begin
//case(r1[11:6]) //s2
case({r1[6],r1[11],r1[7],r1[8],r1[9],r1[10]})
6'b00_1101,6'b01_1001,6'b10_0000,6'b11_1100,
6'b00_1010,6'b01_0101,6'b10_1110,6'b11_0111,
6'b00_0111,6'b01_0010,6'b10_0101,6'b11_0110,
6'b00_0100,6'b01_1100,6'b10_1011,6'b11_1001,
6'b00_0010,6'b01_0110,6'b10_1001,6'b11_0001,
6'b00_1111,6'b01_1011,6'b10_0100,6'b11_0010,
6'b00_1100,6'b01_1000,6'b10_1010,6'b11_1011,
6'b00_0011,6'b01_0111,6'b10_0001,6'b11_1110: s20=1'b0;
default: s20=1'b1;
endcase
case({r1[6],r1[11],r1[7],r1[8],r1[9],r1[10]})
6'b00_1101,6'b01_1001,6'b10_0000,6'b11_1100,
6'b00_0001,6'b01_1010,6'b10_0111,6'b11_0011,
6'b00_0111,6'b01_0010,6'b10_0101,6'b11_0110,
6'b00_1110,6'b01_1111,6'b10_1000,6'b11_1101,
6'b00_0010,6'b01_0110,6'b10_1001,6'b11_0001,
6'b00_1000,6'b01_1101,6'b10_1100,6'b11_1111,
6'b00_1100,6'b01_1000,6'b10_1010,6'b11_1011,
6'b00_1011,6'b01_0001,6'b10_0110,6'b11_0000: s21=1'b0;
default: s21=1'b1;
endcase
case({r1[6],r1[11],r1[7],r1[8],r1[9],r1[10]})
6'b00_1101,6'b01_1001,6'b10_0000,6'b11_1100,
6'b00_0001,6'b01_1010,6'b10_0111,6'b11_0011,
6'b00_1010,6'b01_0101,6'b10_1110,6'b11_0111,
6'b00_0110,6'b01_0000,6'b10_1101,6'b11_0100,
6'b00_0010,6'b01_0110,6'b10_1001,6'b11_0001,
6'b00_1000,6'b01_1101,6'b10_1100,6'b11_1111,
6'b00_1111,6'b01_1011,6'b10_0100,6'b11_0010,
6'b00_0101,6'b01_1110,6'b10_0011,6'b11_1000: s22=1'b0;
default: s22=1'b1;
endcase
case({r1[6],r1[11],r1[7],r1[8],r1[9],r1[10]})
6'b00_1101,6'b01_1001,6'b10_0000,6'b11_1100,
6'b00_0001,6'b01_1010,6'b10_0111,6'b11_0011,
6'b00_1010,6'b01_0101,6'b10_1110,6'b11_0111,
6'b00_0110,6'b01_0000,6'b10_1101,6'b11_0100,
6'b00_0111,6'b01_0010,6'b10_0101,6'b11_0110,
6'b00_1110,6'b01_1111,6'b10_1000,6'b11_1101,
6'b00_0100,6'b01_1100,6'b10_1011,6'b11_1001,
6'b00_1001,6'b01_0011,6'b10_0010,6'b11_1010: s23=1'b0;
default:begin s23=1'b1; end
endcase
end
always @(r1[12:17])
begin
//case(r1[17:12]) //s3
case({r1[12],r1[17],r1[13],r1[14],r1[15],r1[16]})
6'b00_0001,6'b01_0010,6'b10_0111,6'b11_0011,
6'b00_1110,6'b01_1000,6'b10_1010,6'b11_1110,
6'b00_1101,6'b01_0101,6'b10_0010,6'b11_1000,
6'b00_0100,6'b01_0110,6'b10_0001,6'b11_0100,
6'b00_1111,6'b01_1001,6'b10_0100,6'b11_0110,
6'b00_0000,6'b01_0111,6'b10_1101,6'b11_0001,
6'b00_1010,6'b01_1100,6'b10_1011,6'b11_1111,
6'b00_0011,6'b01_1011,6'b10_1110,6'b11_1010: s30=1'b0;
default: s30=1'b1;
endcase
case({r1[12],r1[17],r1[13],r1[14],r1[15],r1[16]})
6'b00_0001,6'b01_0010,6'b10_0111,6'b11_0011,
6'b00_1000,6'b01_1111,6'b10_1001,6'b11_0000,
6'b00_1101,6'b01_0101,6'b10_0010,6'b11_1000,
6'b00_0111,6'b01_1010,6'b10_1100,6'b11_1101,
6'b00_1111,6'b01_1001,6'b10_0100,6'b11_0110,
6'b00_0010,6'b01_0011,6'b10_0011,6'b11_0101,
6'b00_1010,6'b01_1100,6'b10_1011,6'b11_1111,
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