des_ctrl.v

Verilog实现的DES和3-DES

  begin
    if(ready) des3_encrypt_busy<=1'b0; 
    else if(DES3_encrypt_start ||(DES3_decrypt_start &&(CFB || OFB)) )  des3_encrypt_busy<=1'b1;
  end
end


//---------------------------
//3DES decipher busy signal
//---------------------------
always @(posedge clk or negedge rst_n)
begin
  if(!rst_n)
     des3_decrypt_busy<=1'b0;
  else
  if(sw_rst) des3_decrypt_busy<=1'b0;
  else
  begin
     if(ready) des3_decrypt_busy<=1'b0;
     else if(DES3_decrypt_start && (ECB || CBC))  des3_decrypt_busy<=1'b1;
  end
end

//---------------------------
//des_busy signal
//---------------------------
always @(posedge clk or negedge rst_n)
begin
  if(!rst_n) 
  	des_busy<=1'b0;
  else if(sw_rst) des_busy<=1'b0;
       else 
       begin
         if(des_start) des_busy<=1'b1;
	 else if(des_ready) des_busy<=1'b0;
       end
end

//---------------------------
//3des busy signal
//---------------------------
always @ (posedge clk or negedge rst_n)
begin
  if(!rst_n)
  	des3_busy<=1'b0;
  else if(sw_rst) des3_busy<=1'b0;
       else
       begin
          if(des3_start) des3_busy<=1'b1;
          else if(des3_ready) des3_busy<=1'b0;
       end
end
/*****************************************************************/

//---------------------------
//iv_reg back tmp
//---------------------------
reg back_tmp;
always @ (posedge clk or negedge rst_n)
begin
  if(!rst_n) back_tmp<=1'b0;
  else if(sw_rst) back_tmp<=1'b0;
       else
         begin
	    if(ready) back_tmp<=1'b0;
	    else if(CFB && (DES_decrypt_start||DES3_decrypt_start)) back_tmp<=1'b1;
	 end
end


/**************************output signal****************************/
/*
reg countero;
always @(posedge clk or negedge rst_n)
begin
  if(!rst_n) countero<=1'd0;
  else if(sw_rst) countero<=1'd0;
       else 
       begin
         if(des_start ||des3_start) countero<=1'b0;
	 else 
         if(buff_out_load ) countero<=1'd1;
       end
end
*/
//wire sel_left,sel_right;
//assign sel_left=((Left_first && (!countero))||((!Left_first) &&(countero||((!countero)&&((OFB||CFB)&&(s_1||s_8|||s_16||s_32)))))) ;
//assign sel_right=((Left_first && countero)||((!Left_first) &&(!countero)&&(!((OFB||CFB)&&(s_1||s_8|||s_16||s_32)))));

/*******************************************************************/


/**************************whole work mode des and 3des **********/
always @ (posedge clk or negedge rst_n)
begin
  if(!rst_n) 
      des_mode_current_state<=des_mode_idle_state;
  else if(sw_rst) des_mode_current_state<=des_mode_idle_state;
       else des_mode_current_state<=des_mode_next_state;
end
always @ (des_mode_current_state or ECB or CBC or CFB or OFB or DES_encrypt_start or DES_decrypt_start or DES3_encrypt_start or
DES3_decrypt_start or des_encrypt_busy or des_decrypt_busy or des_ready or des3_ready or des3_encrypt_busy or des3_decrypt_busy)
begin
  case(des_mode_current_state)
    des_mode_idle_state:
    		if(ECB&&(DES_encrypt_start||DES_decrypt_start||DES3_encrypt_start||DES3_decrypt_start))
		                    des_mode_next_state = des_mode_buff_2_data_1_state;
		else if(CBC&&(DES_encrypt_start || DES3_encrypt_start))
		                    des_mode_next_state = des_mode_buff_xor_iv_state;
		     else if(CBC&&(DES_decrypt_start || DES3_decrypt_start))
		                    des_mode_next_state = des_mode_buff_2_data_2_state;
		           else if((CFB||OFB)&&(DES_encrypt_start||DES_decrypt_start||DES3_encrypt_start||DES3_decrypt_start))
			                  des_mode_next_state = des_mode_iv_2_data_state;
				else des_mode_next_state = des_mode_idle_state;
    des_mode_buff_2_data_1_state:
    		if(des_encrypt_busy || des_decrypt_busy)
				 des_mode_next_state = des_mode_des_cal_1_state;
		else 
		  des_mode_next_state = des_mode_des3_cal_1_state;
   des_mode_des_cal_1_state:
   		if(des_ready) des_mode_next_state = des_mode_idle_state;
		else des_mode_next_state = des_mode_des_cal_1_state;
   des_mode_des3_cal_1_state:
   		if(des3_ready) des_mode_next_state = des_mode_idle_state;
		else des_mode_next_state = des_mode_des3_cal_1_state;
   des_mode_buff_xor_iv_state:
   		if(des_encrypt_busy) des_mode_next_state = des_mode_des_cal_2_state;
		else
		 des_mode_next_state = des_mode_des3_cal_2_state;
   des_mode_buff_2_data_2_state:
   		if(des_decrypt_busy) des_mode_next_state = des_mode_des_cal_2_state;
		else   des_mode_next_state = des_mode_des3_cal_2_state;
   des_mode_des_cal_2_state:
   		if(des_ready && des_encrypt_busy) des_mode_next_state = des_mode_data_2_iv_state;
		else if(des_ready && des_decrypt_busy) des_mode_next_state = des_mode_data_xor_iv_state;
		      else des_mode_next_state = des_mode_des_cal_2_state;
   des_mode_des3_cal_2_state:
   		if(des3_ready && des3_encrypt_busy) des_mode_next_state = des_mode_data_2_iv_state;
		else if(des3_ready && des3_decrypt_busy) des_mode_next_state = des_mode_data_xor_iv_state;
		     else des_mode_next_state = des_mode_des3_cal_2_state;
   des_mode_data_2_iv_state:
   		des_mode_next_state = des_mode_idle_state;
   des_mode_data_xor_iv_state:
   		des_mode_next_state = des_mode_idle_state;
   des_mode_iv_2_data_state:
                if(des_encrypt_busy || des_decrypt_busy) des_mode_next_state =  des_mode_des_cal_3_state;
		else des_mode_next_state = des_mode_des3_cal_3_state;
		
   des_mode_des_cal_3_state:
              	if(des_ready && CFB) des_mode_next_state = des_mode_tmp_xor_data_state;
		else if(des_ready && OFB) des_mode_next_state = des_mode_iv_back_shift_state;
		     else des_mode_next_state = des_mode_des_cal_3_state;
   des_mode_des3_cal_3_state:
   		if(des3_ready && CFB) des_mode_next_state = des_mode_tmp_xor_data_state;
		else if(des3_ready && OFB) des_mode_next_state = des_mode_iv_back_shift_state;
		     else des_mode_next_state = des_mode_des3_cal_3_state;
   des_mode_tmp_xor_data_state:
            	if(CFB) des_mode_next_state = des_mode_iv_back_shift_state;
		else 	des_mode_next_state = des_mode_idle_state;
   des_mode_iv_back_shift_state:
   		if(OFB) des_mode_next_state = des_mode_tmp_xor_data_state;
		else des_mode_next_state = des_mode_idle_state;
   default: des_mode_next_state = des_mode_idle_state;
  endcase
end

//------------------------------------------------------------------
wire work_idle_state,work_des_cal_1_state,work_des_cal_2_state,work_des_cal_3_state;
wire work_des3_cal_1_state,work_des3_cal_2_state,work_des3_cal_3_state;
assign work_idle_state=(des_mode_current_state==des_mode_idle_state)?1'b1:1'b0;
assign work_des_cal_1_state=(des_mode_current_state==des_mode_des_cal_1_state)?1'b1:1'b0;
assign work_des_cal_2_state=(des_mode_current_state==des_mode_des_cal_2_state)?1'b1:1'b0;
assign work_des_cal_3_state=(des_mode_current_state==des_mode_des_cal_3_state)?1'b1:1'b0;
assign work_des3_cal_1_state=(des_mode_current_state==des_mode_des3_cal_1_state)?1'b1:1'b0;
assign work_des3_cal_2_state=(des_mode_current_state==des_mode_des3_cal_2_state)?1'b1:1'b0;
assign work_des3_cal_3_state=(des_mode_current_state==des_mode_des3_cal_3_state)?1'b1:1'b0;


//------------------------------------------------------------------
//buff_reg to data_reg enable signal
//------------------------------------------------------------------
wire buff_2_data_1_state,buff_2_data_2_state;
wire buff_2_data_1,buff_2_data_2;
		assign buff_2_data_1_state=(des_mode_current_state==des_mode_buff_2_data_1_state)?1'b1:1'b0;
		assign buff_2_data_2_state=(des_mode_current_state==des_mode_buff_2_data_2_state)?1'b1:1'b0;
		assign
buff_2_data_1=(work_idle_state&&ECB&&(DES_encrypt_start||DES_decrypt_start||DES3_encrypt_start||DES3_decrypt_start))?1'b1:1'b0;
		assign buff_2_data_2=(work_idle_state &&CBC&&(DES_decrypt_start || DES3_decrypt_start) )?1'b1:1'b0;
		assign buff_2_data=buff_2_data_1 || buff_2_data_2;
		assign data_sel_buff=buff_2_data ;
		assign tmp_sel_buff=buff_2_data_2 ||iv_2_data;

		
//------------------------------------------------------------------
//des_cal 3des_cal signal
//------------------------------------------------------------------
wire des_cal,des3_cal;
		assign des_cal=(work_des_cal_1_state||
		                work_des_cal_2_state||
				work_des_cal_3_state)?1'b1:1'b0;
				
		assign des3_cal=(work_des3_cal_1_state||
		                work_des3_cal_2_state||
				work_des3_cal_3_state)?1'b1:1'b0;
//------------------------------------------------------------------
//buff xor iv enable signal
//------------------------------------------------------------------
wire buff_xor_iv_state;		
		assign buff_xor_iv=(work_idle_state&&CBC&&(DES_encrypt_start || DES3_encrypt_start))?1'b1:1'b0;
                assign buff_xor_iv_state=(des_mode_current_state==des_mode_buff_xor_iv_state)?1'b1:1'b0;
//------------------------------------------------------------------
//data_reg to  iv_reg enable signal
//------------------------------------------------------------------
wire data_2_iv_state;
		assign data_2_iv_state=(des_mode_current_state==des_mode_data_2_iv_state)?1'b1:1'b0;
		assign data_2_iv=((work_des_cal_2_state&&des_ready && des_encrypt_busy)||
		                  (work_des3_cal_2_state && des3_ready && des3_encrypt_busy) )?1'b1:1'b0;
		assign iv_sel_data=data_2_iv;
//------------------------------------------------------------------
//data xor iv enable signal
//------------------------------------------------------------------
wire data_xor_iv_state;
		assign data_xor_iv_state=(des_mode_current_state==des_mode_data_xor_iv_state)?1'b1:1'b0;
		assign data_xor_iv=((work_des_cal_2_state && des_ready && des_decrypt_busy)||
		                    (work_des3_cal_2_state && des3_ready && des3_decrypt_busy) )?1'b1:1'b0;
		assign iv_sel_tmp=((work_des_cal_2_state && des_ready && des_decrypt_busy)||
		                    (work_des3_cal_2_state && des3_ready && des3_decrypt_busy) )?1'b1:1'b0;
//------------------------------------------------------------------
//iv_reg to data_reg enable signal
//------------------------------------------------------------------
wire iv_2_data_state;
wire tmp_xor_data_state;
		assign iv_2_data_state=(des_mode_current_state==des_mode_iv_2_data_state)?1'b1:1'b0;
		assign iv_2_data=(work_idle_state &&(CFB||OFB)&&(DES_encrypt_start||DES_decrypt_start||DES3_encrypt_start||DES3_decrypt_start) )?1'b1:1'b0;
		assign data_sel_iv=iv_2_data;
//------------------------------------------------------------------
//iv_reg shift enable signal
//------------------------------------------------------------------
wire iv_shift_state;
                assign iv_shift=((work_des3_cal_3_state && des3_ready && OFB)||(work_des_cal_3_state && des_ready &&
		OFB)||(tmp_xor_data_state && CFB ))?1'b1:1'b0;
		assign iv_shift_state=(des_mode_current_state==des_mode_iv_back_shift_state)?1'b1:1'b0;
		assign iv_shift_1=(iv_shift && s_1)?1'b1:1'b0;
		assign iv_shift_8=(iv_shift && s_8)?1'b1:1'b0;
		assign iv_shift_16=(iv_shift && s_16)?1'b1:1'b0;
		assign iv_shift_32=(iv_shift && s_32)?1'b1:1'b0;
		assign iv_shift_64=(iv_shift && s_64)?1'b1:1'b0;
		assign iv_back_tmp=back_tmp && iv_shift;
//------------------------------------------------------------------
//tmp_reg xor data_reg enable signal
//------------------------------------------------------------------

		assign tmp_xor_data=((work_des3_cal_3_state &&des3_ready && CFB)||(work_des_cal_3_state &&des_ready && CFB
		)||(iv_shift_state&& OFB ) )?1'b1:1'b0;
		assign tmp_xor_data_state=(des_mode_current_state==des_mode_tmp_xor_data_state)?1'b1:1'b0;
		assign tmp_xor_data_1=(tmp_xor_data && s_1)?1'b1:1'b0;
		assign tmp_xor_data_8=(tmp_xor_data && s_8)?1'b1:1'b0;
		assign tmp_xor_data_16=(tmp_xor_data && s_16)?1'b1:1'b0;
		assign tmp_xor_data_32=(tmp_xor_data && s_32)?1'b1:1'b0;
		assign tmp_xor_data_64=(tmp_xor_data && s_64)?1'b1:1'b0;
//------------------------------------------------------------------
//des start signal
//------------------------------------------------------------------
assign des_start=(des3_start||(des_ready&(des1_state||des2_state))|| 
                 ((des_encrypt_busy||des_decrypt_busy)&&(buff_2_data_1_state||buff_2_data_2_state||buff_xor_iv_state||iv_2_data_state))
		 )?1'b1:1'b0;


assign key_sel_k1=(((des_encrypt_busy || des_decrypt_busy) && des_start)||
                    (des3_encrypt_busy&&des3_start)||
		    (des3_decrypt_busy && des_ready && des2_state))?1'b1:1'b0;
assign key_sel_k2=(des1_state && des_ready)?1'b1:1'b0;	
assign key_sel_k3=((des3_encrypt_busy && des_ready && des2_state)||
                    (des3_decrypt_busy && des3_start))? 1'b1:1'b0;			     
//------------------------------------------------------------------
//3des start signal
//------------------------------------------------------------------
assign des3_start=((buff_2_data_1_state||buff_2_data_2_state||buff_xor_iv_state||iv_2_data_state)&&
                   (des3_encrypt_busy||des3_decrypt_busy))?1'b1:1'b0;


//------------------------------------------------------------------
//ready signal
//------------------------------------------------------------------
		assign ready=(((work_des_cal_1_state)&&des_ready)||
		               ((work_des3_cal_1_state)&&des3_ready)||
			       (work_des_cal_2_state && des_ready&&des_encrypt_busy)||
			       (work_des3_cal_2_state && des3_ready && des3_encrypt_busy)||
			       data_xor_iv_state||
			       tmp_xor_data_state 
			        )?1'b1:1'b0;



/*****************************************************************/


/**************************3des fsm******************************/
always @ (posedge clk or negedge rst_n)
begin
  if(!rst_n)
  	des3_current_state<=des3_idle_state;
  else if(sw_rst) des3_current_state<=des3_idle_state;
       else des3_current_state<=des3_next_state;
end

always @(des3_current_state or des3_start or des_ready )
begin
  case(des3_current_state)
    des3_idle_state:
    		if(des3_start)	des3_next_state = des3_des1_state;
		else des3_next_state = des3_idle_state;
    des3_des1_state:
    		if(des_ready) 	des3_next_state = des3_des2_state;
		else des3_next_state = des3_des1_state;
    des3_des2_state:
    		if(des_ready)	des3_next_state = des3_des3_state;