shift_add_tb_settings.txt

移向相加器

[SETTINGS]
UUT_module%shift_add%
TB_module%shift_add_tb%
DSN_PATH%$DSN\src\TestBench%
OUTPUT_DIRECTORY%D:\demo\demo21\src\TestBench%
STIMULUS%NO%
VECTORS_FILE%%
AWF_FILE%%
TB_FILE%shift_add_TB.v%
MACRO_FILE%shift_add_TB_runtest.do%
UUT_module_FILE%demo21/src/shift_add.v%
LIBRARY_NAME%demo21%
LIBRARY_TYPE%work%
TestBench_TYPE%simple%
ENABLE_FILE%none%

[GENERICS]

[PORTS]
product%out%[15:0]reg%NO%NOCLK%
a%in%[7:0]wire%NO%NOCLK%
b%in%[7:0]wire%NO%NOCLK%
clk%in%wire%NO%NOCLK%

[SDF]

[INCLUDE]
[Verilog_FILES]
$DSN\src\shift_add.v