shift_add.v

来自「移向相加器」· Verilog 代码 · 共 59 行

//--------------------------------------------------------------------------------------------------
//
// Title       : shift_add
// Design      : demo21
// Author      : suli
// Company     : Tsinghua
//
//-------------------------------------------------------------------------------------------------
//
// File        : shift_add.v
// Generated   : Sat Dec 13 10:57:29 2003
// From        : interface description file
// By          : Itf2Vhdl ver. 1.20
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------
`timescale 1ps / 1ps

//{{ Section below this comment is automatically maintained
//   and may be overwritten
//{module {shift_add}}
module shift_add ( product, a, b, clk, reset );
	output[15:0] product;
	input[7:0]a,b;
	input clk, reset;
	reg[15:0] product,tempa;
	reg[7:0] tempb;
	reg qb;
	integer i;
	
	always@(negedge reset or posedge clk)
		if (~reset)
			begin
				tempa[15:8]=7'd0;
				tempa[7:0]=a;
				tempb=b;
				product=16'd0;
				i=0;
			end
		else		
			begin 
				qb=tempb[0];
				tempb[6:0]=tempb[7:1];
				if (qb==1)  product=product+tempa;
				tempa=tempa<<1;
				i=i+1;
			end



//}} End of automatically maintained section

// -- Enter your statements here -- //

endmodule