shift_add_tb.v

来自「移向相加器」· Verilog 代码 · 共 55 行

//--------------------------------------------------------------------------------------------------
//
// Title       : shift_add_tb
// Design      : demo21
// Author      : suli
// Company     : Tsinghua
//
//-------------------------------------------------------------------------------------------------
//
// File        : shift_add_TB.v
// Generated   : Sat Dec 13 11:06:26 2003
// From        : shift_add_TB_settings.txt
// By          : tb_verilog.pl ver. ver 1.2s
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------

`timescale 1ns / 1ns
module shift_add_tb;


//Internal signals declarations:
wire [15:0]product;
reg [7:0]a;
reg [7:0]b;
reg clk, reset;



// Unit Under Test port map
	shift_add UUT (
		.product(product),
		.a(a),
		.b(b),
		.clk(clk),
		.reset(reset));

initial
//	$monitor($realtime,,"ps %h %h %h %h ",product,a,b,clk);
	begin
		clk=0;
		a=8'd10;
		b=8'b10000000;
		reset=0;
		#120 reset=1;
	end

always 
	clk=#25 ~clk; 

endmodule