tb_medfilter_vhd.vhd

用VHDL实现了Matlab中MedFilt1函数3阶中值滤波。进行排序时没有用软件使用的排序法

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_arith.all;

use IEEE.STD_LOGIC_ARITH.conv_std_logic_vector;
use IEEE.STD_LOGIC_ARITH.conv_integer;
use std.textio.all; 
ENTITY tb_MedFilter_VHD IS
END tb_MedFilter_VHD;
 
ARCHITECTURE behavior OF tb_MedFilter_VHD IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT MedFilter_VHD
    PORT(
         clk : IN  std_logic;
         rst : IN  std_logic;
         nd : IN  std_logic;
         din : IN  std_logic_vector(15 downto 0);
         rdy : OUT  std_logic;
         dout : OUT  std_logic_vector(15 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal clk : std_logic := '0';
   signal rst : std_logic := '0';
   signal nd : std_logic := '0';
   signal din : std_logic_vector(15 downto 0) := (others => '0');

 	--Outputs
   signal rdy : std_logic;
   signal dout : std_logic_vector(15 downto 0);

   -- Clock period definitions
   constant clk_period : time := 10 ns;
	
--type send_data is array integer range <lower_limit> to <upper_limit>;	
 
 signal send_cnt :std_logic_vector(15 downto 0):=(others=>'0');
 signal nd_cnt : std_logic_vector(3 downto 0):=x"0";
   signal ndr : std_logic;
   signal go : std_logic:='0';
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: MedFilter_VHD PORT MAP (
          clk => clk,
          rst => rst,
          nd => nd,
          din => din,
          rdy => rdy,
          dout => dout
        );

-- Clock process definitions
clk_process :process
begin
	clk <= '0';
	wait for clk_period/2;
	clk <= '1';
	wait for clk_period/2;
end process;


process(clk)
begin
	if (clk'event and clk = '1') then
		if nd_cnt = x"3" then
			nd_cnt <= x"0";
			ndr <= '1';
		else
			nd_cnt <= nd_cnt + 1;
			ndr <= '0';
		end if;
	end if;
end process;
 
process(clk)
begin
	if (clk'event and clk = '1') then
		nd <= ndr;
		if go = '1' then
			if (ndr = '1') then
				case send_cnt is
					when x"0000" =>
						send_cnt <= send_cnt + 1;
						din <= CONV_STD_LOGIC_VECTOR(4,16);
					when x"0001" =>
						send_cnt <= send_cnt + 1;
						din <= CONV_STD_LOGIC_VECTOR(-3,16);
					when x"0002" =>
						send_cnt <= send_cnt + 1;
						din <= CONV_STD_LOGIC_VECTOR(5,16);		
					when x"0003" =>
						send_cnt <= send_cnt + 1;
						din <= CONV_STD_LOGIC_VECTOR(2,16);			
					when x"0004" =>
						send_cnt <= send_cnt + 1;
						din <= CONV_STD_LOGIC_VECTOR(8,16);			
					when x"0005" =>
						send_cnt <= send_cnt + 1;
						din <= CONV_STD_LOGIC_VECTOR(9,16);			
					when x"0006" =>
--						send_cnt <= x"0000";
						send_cnt <= send_cnt + 1;
						din <= CONV_STD_LOGIC_VECTOR(1,16);			
					when others=> 
						send_cnt <= send_cnt + 1;
						din <= CONV_STD_LOGIC_VECTOR(500,16);			
				end case;
			end if;
		end if;
	end if;
end process;



process
begin

rst <= '1';
go <= '0';
wait for 20*clk_period;
rst <= '0';
go <='1';
--wait for 1ms;
wait;

end process;




END;