tb_uart.tbw

来自「一种实现计算机接口rs232与FPGA通信的基于VHDL语言设计的一段非常简洁的」· TBW 代码 · 共 66 行

version 3
f:\data file\uart01\uart.vhd
top
VHDL
VHDL
tb_uart.xwv
Clocked
-
-
90000000000
ns
GSR:false
PRLD:false
100000000
CLOCK_LIST_BEGIN
clk32mhz
100000000
100000000
15000000
15000000
0
RISING
CLOCK_LIST_END
SIGNAL_LIST_BEGIN
rec_buf
clk32mhz
rec_ready
clk32mhz
reset
clk32mhz
rxd
clk32mhz
txd_done_out
clk32mhz
txd_out
clk32mhz
txdbuf_in
clk32mhz
xmit_cmd_p_in
clk32mhz
SIGNAL_LIST_END
SIGNALS_NOT_ON_DISPLAY
clkout_DIFF
rec_buf_DIFF
rec_ready_DIFF
txd_done_out_DIFF
txd_out_DIFF
SIGNALS_NOT_ON_DISPLAY_END
MARKER_LIST_BEGIN
MARKER_LIST_END
MEASURE_LIST_BEGIN
MEASURE_LIST_END
SIGNAL_ORDER_BEGIN
clk32mhz
reset
rxd
xmit_cmd_p_in
txdbuf_in
rec_ready
txd_done_out
txd_out
rec_buf
SIGNAL_ORDER_END
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