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一种实现计算机接口rs232与FPGA通信的基于VHDL语言设计的一段非常简洁的程序

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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "F:/data file/uart01/baud.vhd" in Library work.
ERROR:HDLParsers:164 - "F:/data file/uart01/baud.vhd" Line 22. parse error, unexpected EQ
WARNING:HDLParsers:3481 - Library work has no units. Did not save reference file "xst/work/hdllib.ref" for it.
--> 

Total memory usage is 76240 kilobytes

Number of errors   :    1 (   0 filtered)
Number of warnings :    1 (   0 filtered)
Number of infos    :    0 (   0 filtered)

ERROR: XST failed
Process "Synthesize" did not complete.


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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "F:/data file/uart01/baud.vhd" in Library work.
Entity <baud> compiled.
Entity <baud> (Architecture <behavioral>) compiled.
Compiling vhdl file "F:/data file/uart01/reciever.vhd" in Library work.
ERROR:HDLParsers:164 - "F:/data file/uart01/reciever.vhd" Line 20. parse error, unexpected EQ
--> 

Total memory usage is 76240 kilobytes

Number of errors   :    1 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)

ERROR: XST failed
Process "Synthesize" did not complete.


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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "F:/data file/uart01/baud.vhd" in Library work.
Architecture behavioral of Entity baud is up to date.
Compiling vhdl file "F:/data file/uart01/reciever.vhd" in Library work.
Entity <reciever> compiled.
Entity <reciever> (Architecture <behavioral>) compiled.
Compiling vhdl file "F:/data file/uart01/transfer.vhd" in Library work.
ERROR:HDLParsers:164 - "F:/data file/uart01/transfer.vhd" Line 19. parse error, unexpected EQ
--> 

Total memory usage is 76240 kilobytes

Number of errors   :    1 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)

ERROR: XST failed
Process "Synthesize" did not complete.


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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "F:/data file/uart01/baud.vhd" in Library work.
Architecture behavioral of Entity baud is up to date.
Compiling vhdl file "F:/data file/uart01/reciever.vhd" in Library work.
Architecture behavioral of Entity reciever is up to date.
Compiling vhdl file "F:/data file/uart01/transfer.vhd" in Library work.
Entity <transfer> compiled.
Entity <transfer> (Architecture <behavioral>) compiled.
Compiling vhdl file "F:/data file/uart01/uart.vhd" in Library work.
Entity <top> compiled.
Entity <top> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top> (Architecture <behavioral>).
WARNING:Xst:1542 - "F:/data file/uart01/uart.vhd" line 56: No default binding for component: <reciever>. Generic <framlenr> is not on the component.
WARNING:Xst:1542 - "F:/data file/uart01/uart.vhd" line 58: No default binding for component: <transfer>. Generic <framlent> is not on the component.
Entity <top> analyzed. Unit <top> generated.

Analyzing Entity <baud> (Architecture <behavioral>).
Entity <baud> analyzed. Unit <baud> generated.

Analyzing Entity <reciever> (Architecture <behavioral>).
Entity <reciever> analyzed. Unit <reciever> generated.

Analyzing Entity <transfer> (Architecture <behavioral>).
Entity <transfer> analyzed. Unit <transfer> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <transfer>.
    Related source file is "F:/data file/uart01/transfer.vhd".
WARNING:Xst:1780 - Signal <tcnt> is never used or assigned.
    Found finite state machine <FSM_0> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 5                                              |
    | Transitions        | 11                                             |
    | Inputs             | 4                                              |
    | Outputs            | 5                                              |
    | Clock              | bclkt (rising_edge)                            |
    | Reset              | resett (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | x_idle                                         |
    | Power Up State     | x_idle                                         |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <txd_done>.
    Found 5-bit comparator greatequal for signal <$n0006> created at line 55.
    Found 5-bit comparator greatequal for signal <$n0007> created at line 58.
    Found 5-bit adder for signal <$n0018> created at line 51.
    Found 32-bit adder for signal <$n0019> created at line 65.
    Found 1-bit register for signal <txds>.
    Found 32-bit register for signal <xbitcnt>.
    Found 5-bit register for signal <xcnt16>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  39 D-type flip-flop(s).
	inferred   2 Adder/Subtractor(s).
	inferred   2 Comparator(s).
Unit <transfer> synthesized.


Synthesizing Unit <reciever>.
    Related source file is "F:/data file/uart01/reciever.vhd".
    Found finite state machine <FSM_1> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 5                                              |
    | Transitions        | 10                                             |
    | Inputs             | 4                                              |
    | Outputs            | 5                                              |
    | Clock              | bclkr (rising_edge)                            |
    | Reset              | resetr (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | r_start                                        |
    | Power Up State     | r_start                                        |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 8-bit register for signal <rbuf>.
    Found 1-bit register for signal <r_ready>.
    Found 4-bit comparator greatequal for signal <$n0006> created at line 68.
    Found 4-bit adder for signal <$n0025> created at line 57.
    Found 32-bit adder for signal <$n0026> created at line 75.
    Found 4-bit register for signal <count>.
    Found 8-bit register for signal <rbufs>.
    Found 32-bit register for signal <rcnt>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  53 D-type flip-flop(s).
	inferred   2 Adder/Subtractor(s).
	inferred   1 Comparator(s).
Unit <reciever> synthesized.


Synthesizing Unit <baud>.
    Related source file is "F:/data file/uart01/baud.vhd".
    Found 1-bit register for signal <bclk>.
    Found 32-bit comparator greatequal for signal <$n0002> created at line 41.
    Found 32-bit up counter for signal <cnt>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
	inferred   1 Comparator(s).
Unit <baud> synthesized.


Synthesizing Unit <top>.
    Related source file is "F:/data file/uart01/uart.vhd".
Unit <top> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Analyzing FSM <FSM_1> for best encoding.
Optimizing FSM <FSM_1> on signal <state[1:3]> with sequential encoding.
----------------------
 State    | Encoding
----------------------
 r_start  | 000
 r_center | 001
 r_wait   | 010
 r_sample | 100
 r_stop   | 011
----------------------
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <FSM_0> on signal <state[1:5]> with speed1 encoding.
---------------------
 State   | Encoding
---------------------
 x_idle  | 10000
 x_start | 01000
 x_wait  | 00100
 x_shift | 00001
 x_stop  | 00010
---------------------
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 2
# Adders/Subtractors               : 4
 32-bit adder                      : 2
 4-bit adder                       : 1
 5-bit adder                       : 1
# Counters                         : 1
 32-bit up counter                 : 1
# Registers                        : 25
 1-bit register                    : 20
 32-bit register                   : 2
 4-bit register                    : 1
 5-bit register                    : 1
 8-bit register                    : 1
# Comparators                      : 4
 32-bit comparator greatequal      : 1
 4-bit comparator greatequal       : 1
 5-bit comparator greatequal       : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <top> ...

Optimizing unit <transfer> ...
WARNING:Xst:1293 - FF/Latch  <xcnt16_4> has a constant value of 0 in block <transfer>.

Optimizing unit <reciever> ...
Loading device for application Rf_Device from file '3s400.nph' in environment C:/Xilinx/.xinstall.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block top, actual ratio is 4.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-4 

 Number of Slices:                     145  out of   3584     4%  
 Number of Slice Flip Flops:           133  out of   7168     1%  
 Number of 4 input LUTs:               258  out of   7168     3%  
 Number of bonded IOBs:                 23  out of    141    16%  
 Number of GCLKs:                        2  out of      8    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk32mhz                           | BUFGP                  | 33    |
u1/bclk:Q                          | BUFG                   | 100   |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 10.126ns (Maximum Frequency: 98.760MHz)
   Minimum input arrival time before clock: 6.289ns
   Maximum output required time after clock: 7.241ns
   Maximum combinational path delay: No path found

=========================================================================


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