transcript

一种实现计算机接口rs232与FPGA通信的基于VHDL语言设计的一段非常简洁的程序

# Reading D:/Modeltech_6.1f/tcl/vsim/pref.tcl 
# //  ModelSim SE 6.1f May 12 2006 
# //
# //  Copyright 2006 Mentor Graphics Corporation
# //              All Rights Reserved.
# //
# //  THIS WORK CONTAINS TRADE SECRET AND 
# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# //  AND IS SUBJECT TO LICENSE TERMS.
# //
# do tb_uart.fdo 
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 6.1f Compiler 2006.05 May 12 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity baud
# -- Compiling architecture behavioral of baud
# Model Technology ModelSim SE vcom 6.1f Compiler 2006.05 May 12 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity reciever
# -- Compiling architecture behavioral of reciever
# Model Technology ModelSim SE vcom 6.1f Compiler 2006.05 May 12 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity transfer
# -- Compiling architecture behavioral of transfer
# Model Technology ModelSim SE vcom 6.1f Compiler 2006.05 May 12 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity top
# -- Compiling architecture behavioral of top
# Model Technology ModelSim SE vcom 6.1f Compiler 2006.05 May 12 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity tb_uart
# -- Compiling architecture testbench_arch of tb_uart
# vsim -lib work -t 1ps tb_uart 
# Loading d:\Modeltech_6.1f\win32/../std.standard
# Loading d:\Modeltech_6.1f\win32/../ieee.std_logic_1164(body)
# Loading d:\Modeltech_6.1f\win32/../ieee.std_logic_arith(body)
# Loading d:\Modeltech_6.1f\win32/../ieee.std_logic_unsigned(body)
# Loading d:\Modeltech_6.1f\win32/../std.textio(body)
# Loading d:\Modeltech_6.1f\win32/../ieee.std_logic_textio(body)
# Loading work.tb_uart(testbench_arch)
# Loading work.top(behavioral)
# Loading work.baud(behavioral)
# Loading work.reciever(behavioral)
# Loading work.transfer(behavioral)
# .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs.pw.wf
# .main_pane.workspace
# .main_pane.signals.interior.cs
# ** Failure: Simulation successful (not a failure).  No problems detected.
#    Time: 90200 ns  Iteration: 0  Process: /tb_uart/line__91 File: tb_uart.vhw
# Break at tb_uart.vhw line 1403
# Simulation Breakpoint: Break at tb_uart.vhw line 1403
# MACRO ./tb_uart.fdo PAUSED at line 16