transfer.vhd

一种实现计算机接口rs232与FPGA通信的基于VHDL语言设计的一段非常简洁的程序

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-- Company: 
-- Engineer:
--
-- Create Date:    17:41:55 03/13/09
-- Design Name:    
-- Module Name:    transfer - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
--===============================================================================
--说明：由五个状态（x_idle,x_start,x_wait,x_shift,x_stop）和一个进程构成
--最后修改时间：2003年7月10日
--===============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity transfer is
    generic(framlent:integer:=8);
    Port (bclkt		:in std_logic;
	       resett		:in std_logic;
			 xmit_cmd_p :in std_logic;                       --定义输入输出信号
          txdbuf     :in std_logic_vector(7 downto 0):="11001010";
          txd        :out std_logic;
          txd_done   :out std_logic);
end transfer;
 
architecture behavioral of transfer is
type states is (x_idle,x_start,x_wait,x_shift,x_stop);                      --定义个子状态
signal state:states:=x_idle;
signal tcnt:integer:=0;

begin
 
process(bclkt,resett,xmit_cmd_p,txdbuf)                            --主控时序、组合进程
variable xcnt16:std_logic_vector(4 downto 0):="00000";                  --定义中间变量
variable xbitcnt:integer:=0;
variable txds:std_logic;
 
begin 
  if resett='1' then                                                 --复位
     state<=x_idle; txd_done<='0'; txds:='1';
  elsif rising_edge(bclkt) then
     case state is
       when x_idle=>if xmit_cmd_p='1' then
		               state<=x_start; txd_done<='0';                                 
                    else state<=x_idle;                  --状态1，等待数据帧发送命令
                    end if;
       when x_start=>if xcnt16>="01111" then
		                  state<=x_wait; xcnt16:="00000";
                      else xcnt16:=xcnt16+1; txds:='0'; state<=x_start;
                     end if;                          --状态2，发送信号至起始位
       when x_wait=>if xcnt16>="01110" then
                       if xbitcnt=framlent then 
							  state<=x_stop; xbitcnt:=0;
                       else state<=x_shift;
                       end if;
                       xcnt16:="00000";
                     else xcnt16:=xcnt16+1; state<=x_wait;
                     end if;                     --状态3，等待状态
       when x_shift=>txds:=txdbuf(xbitcnt); xbitcnt:=xbitcnt+1; state<=x_wait;                                                                    --状态4，将待发数据进行并串转换
       when x_stop=>if xcnt16>="01111" then
                       if xmit_cmd_p='0' then 
							     state<=x_idle; xcnt16:="00000";
                       else xcnt16:=xcnt16; state<=x_stop;
                       end if; txd_done<='1';
                     else xcnt16:=xcnt16+1; txds:='1'; state<=x_stop;
                     end if;                      --状态5，停止位发送状态
       when others=>state<=x_idle;
       end case;         
  end if;
  txd<=txds;
end process;
 
end behavioral;