hdpdeps.ref

一种实现计算机接口rs232与FPGA通信的基于VHDL语言设计的一段非常简洁的程序

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FL "F:/data file/uart01/baud.vhd" 2009/03/13.21:39:06 H.42
EN work/BAUD 1236951640            FL "F:/data file/uart01/baud.vhd" PB ieee/STD_LOGIC_1164 1106404628 \
      PB ieee/STD_LOGIC_ARITH 1106404630 PB ieee/STD_LOGIC_UNSIGNED 1106404634
AR work/BAUD/BEHAVIORAL 1236951641 FL "F:/data file/uart01/baud.vhd" EN work/BAUD 1236951640
FL "F:/data file/uart01/transfer.vhd" 2009/03/13.21:40:26 H.42
EN work/TRANSFER 1236951644        FL "F:/data file/uart01/transfer.vhd" \
      PB ieee/STD_LOGIC_1164 1106404628 PB ieee/STD_LOGIC_ARITH 1106404630 \
      PB ieee/STD_LOGIC_UNSIGNED 1106404634
AR work/TRANSFER/BEHAVIORAL 1236951645 FL "F:/data file/uart01/transfer.vhd" \
      EN work/TRANSFER 1236951644
FL "F:/data file/uart01/uart.vhd" 2009/03/13.21:40:38 H.42
EN work/TOP 1236951646             FL "F:/data file/uart01/uart.vhd" PB ieee/STD_LOGIC_1164 1106404628 \
      PB ieee/STD_LOGIC_ARITH 1106404630 PB ieee/STD_LOGIC_UNSIGNED 1106404634
AR work/TOP/BEHAVIORAL 1236951647  FL "F:/data file/uart01/uart.vhd" EN work/TOP 1236951646 \
      CP BAUD           CP RECIEVER       CP TRANSFER
FL "F:/data file/uart01/reciever.vhd" 2009/03/13.21:39:42 H.42
EN work/RECIEVER 1236951642        FL "F:/data file/uart01/reciever.vhd" \
      PB ieee/STD_LOGIC_1164 1106404628 PB ieee/STD_LOGIC_ARITH 1106404630 \
      PB ieee/STD_LOGIC_UNSIGNED 1106404634
AR work/RECIEVER/BEHAVIORAL 1236951643 FL "F:/data file/uart01/reciever.vhd" \
      EN work/RECIEVER 1236951642