top.syr

一种实现计算机接口rs232与FPGA通信的基于VHDL语言设计的一段非常简洁的程序

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <top> ...

Optimizing unit <transfer> ...
WARNING:Xst:1293 - FF/Latch  <xcnt16_4> has a constant value of 0 in block <transfer>.

Optimizing unit <reciever> ...
Loading device for application Rf_Device from file '3s400.nph' in environment C:/Xilinx/.xinstall.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block top, actual ratio is 4.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : top.ngr
Top Level Output File Name         : top
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 23

Macro Statistics :
# Registers                        : 17
#      1-bit register              : 12
#      32-bit register             : 2
#      4-bit register              : 1
#      5-bit register              : 1
#      8-bit register              : 1
# Counters                         : 1
#      32-bit up counter           : 1
# Adders/Subtractors               : 2
#      32-bit adder                : 2
# Comparators                      : 4
#      32-bit comparator greatequal: 1
#      4-bit comparator greatequal : 1
#      5-bit comparator greatequal : 2

Cell Usage :
# BELS                             : 469
#      GND                         : 1
#      INV                         : 5
#      LUT1                        : 14
#      LUT1_L                      : 50
#      LUT2                        : 6
#      LUT2_L                      : 27
#      LUT3                        : 10
#      LUT3_D                      : 1
#      LUT3_L                      : 22
#      LUT4                        : 58
#      LUT4_D                      : 6
#      LUT4_L                      : 64
#      MUXCY                       : 104
#      MUXF5                       : 6
#      VCC                         : 1
#      XORCY                       : 94
# FlipFlops/Latches                : 133
#      FDC                         : 13
#      FDCPE                       : 32
#      FDE                         : 86
#      FDP                         : 2
# Clock Buffers                    : 2
#      BUFG                        : 1
#      BUFGP                       : 1
# IO Buffers                       : 22
#      IBUF                        : 11
#      OBUF                        : 11
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-4 

 Number of Slices:                     145  out of   3584     4%  
 Number of Slice Flip Flops:           133  out of   7168     1%  
 Number of 4 input LUTs:               258  out of   7168     3%  
 Number of bonded IOBs:                 23  out of    141    16%  
 Number of GCLKs:                        2  out of      8    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk32mhz                           | BUFGP                  | 33    |
u1/bclk:Q                          | BUFG                   | 100   |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 10.126ns (Maximum Frequency: 98.760MHz)
   Minimum input arrival time before clock: 6.289ns
   Maximum output required time after clock: 7.241ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk32mhz'
  Clock period: 10.126ns (frequency: 98.760MHz)
  Total number of paths / destination ports: 16236 / 33
-------------------------------------------------------------------------
Delay:               10.126ns (Levels of Logic = 45)
  Source:            u1/cnt_4 (FF)
  Destination:       u1/cnt_31 (FF)
  Source Clock:      clk32mhz rising
  Destination Clock: clk32mhz rising

  Data Path: u1/cnt_4 to u1/cnt_31
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCPE:C->Q            2   0.720   1.216  u1/cnt_4 (u1/cnt_4)
     LUT1_L:I0->LO         1   0.551   0.000  u1/cnt_4_rt (u1/cnt_4_rt)
     MUXCY:S->O            1   0.500   0.000  Andcy (And_cyo)
     MUXCY:CI->O           1   0.064   0.000  norcy (nor_cyo)
     MUXCY:CI->O           1   0.064   0.000  Andcy_rn_0 (And_cyo1)
     MUXCY:CI->O           1   0.064   0.000  norcy_rn_0 (nor_cyo1)
     MUXCY:CI->O           1   0.064   0.000  norcy_rn_1 (nor_cyo2)
     MUXCY:CI->O           1   0.064   0.000  norcy_rn_2 (nor_cyo3)
     MUXCY:CI->O           1   0.064   0.000  norcy_rn_3 (nor_cyo4)
     MUXCY:CI->O           1   0.064   0.000  norcy_rn_4 (nor_cyo5)
     MUXCY:CI->O           1   0.064   0.000  norcy_rn_5 (nor_cyo6)
     MUXCY:CI->O          34   0.281   2.204  GE_stagecy (u1/_n0002)
     LUT1_L:I0->LO         1   0.551   0.000  u1/_n0002_rt (u1/_n0002_rt)
     MUXCY:S->O            1   0.500   0.000  u1/cnt_inst_cy_0 (u1/cnt_inst_cy_0)
     MUXCY:CI->O           1   0.064   0.000  u1/cnt_inst_cy_1 (u1/cnt_inst_cy_1)
     MUXCY:CI->O           1   0.064   0.000  u1/cnt_inst_cy_2 (u1/cnt_inst_cy_2)
     MUXCY:CI->O           1   0.064   0.000  u1/cnt_inst_cy_3 (u1/cnt_inst_cy_3)
     MUXCY:CI->O           1   0.064   0.000  u1/cnt_inst_cy_4 (u1/cnt_inst_cy_4)
     MUXCY:CI->O           1   0.064   0.000  u1/cnt_inst_cy_5 (u1/cnt_inst_cy_5)
     MUXCY:CI->O           1   0.064   0.000  u1/cnt_inst_cy_6 (u1/cnt_inst_cy_6)
     MUXCY:CI->O           1   0.064   0.000  u1/cnt_inst_cy_7 (u1/cnt_inst_cy_7)
     MUXCY:CI->O           1   0.064   0.000  u1/cnt_inst_cy_8 (u1/cnt_inst_cy_8)
     MUXCY:CI->O           1   0.064   0.000  u1/cnt_inst_cy_9 (u1/cnt_inst_cy_9)
     MUXCY:CI->O           1   0.064   0.000  u1/cnt_inst_cy_10 (u1/cnt_inst_cy_10)
     MUXCY:CI->O           1   0.064   0.000  u1/cnt_inst_cy_11 (u1/cnt_inst_cy_11)
     MUXCY:CI->O           1   0.064   0.000  u1/cnt_inst_cy_12 (u1/cnt_inst_cy_12)
     MUXCY:CI->O           1   0.064   0.000  u1/cnt_inst_cy_13 (u1/cnt_inst_cy_13)
     MUXCY:CI->O           1   0.064   0.000  u1/cnt_inst_cy_14 (u1/cnt_inst_cy_14)
     MUXCY:CI->O           1   0.064   0.000  u1/cnt_inst_cy_15 (u1/cnt_inst_cy_15)
     MUXCY:CI->O           1   0.064   0.000  u1/cnt_inst_cy_16 (u1/cnt_inst_cy_16)
     MUXCY:CI->O           1   0.064   0.000  u1/cnt_inst_cy_17 (u1/cnt_inst_cy_17)
     MUXCY:CI->O           1   0.064   0.000  u1/cnt_inst_cy_18 (u1/cnt_inst_cy_18)
     MUXCY:CI->O           1   0.064   0.000  u1/cnt_inst_cy_19 (u1/cnt_inst_cy_19)
     MUXCY:CI->O           1   0.064   0.000  u1/cnt_inst_cy_20 (u1/cnt_inst_cy_20)
     MUXCY:CI->O           1   0.064   0.000  u1/cnt_inst_cy_21 (u1/cnt_inst_cy_21)
     MUXCY:CI->O           1   0.064   0.000  u1/cnt_inst_cy_22 (u1/cnt_inst_cy_22)
     MUXCY:CI->O           1   0.064   0.000  u1/cnt_inst_cy_23 (u1/cnt_inst_cy_23)
     MUXCY:CI->O           1   0.064   0.000  u1/cnt_inst_cy_24 (u1/cnt_inst_cy_24)
     MUXCY:CI->O           1   0.064   0.000  u1/cnt_inst_cy_25 (u1/cnt_inst_cy_25)
     MUXCY:CI->O           1   0.064   0.000  u1/cnt_inst_cy_26 (u1/cnt_inst_cy_26)
     MUXCY:CI->O           1   0.064   0.000  u1/cnt_inst_cy_27 (u1/cnt_inst_cy_27)
     MUXCY:CI->O           1   0.064   0.000  u1/cnt_inst_cy_28 (u1/cnt_inst_cy_28)
     MUXCY:CI->O           1   0.064   0.000  u1/cnt_inst_cy_29 (u1/cnt_inst_cy_29)
     MUXCY:CI->O           1   0.064   0.000  u1/cnt_inst_cy_30 (u1/cnt_inst_cy_30)
     MUXCY:CI->O           0   0.064   0.000  u1/cnt_inst_cy_31 (u1/cnt_inst_cy_31)
     XORCY:CI->O           1   0.904   0.000  u1/cnt_inst_sum_31 (u1/cnt_inst_sum_31)
     FDCPE:D                   0.203          u1/cnt_31
    ----------------------------------------
    Total                     10.126ns (6.706ns logic, 3.420ns route)
                                       (66.2% logic, 33.8% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'u1/bclk:Q'
  Clock period: 9.117ns (frequency: 109.685MHz)
  Total number of paths / destination ports: 2082 / 108
-------------------------------------------------------------------------
Delay:               9.117ns (Levels of Logic = 6)
  Source:            u2/rcnt_30 (FF)
  Destination:       u2/state_FFd3 (FF)
  Source Clock:      u1/bclk:Q rising
  Destination Clock: u1/bclk:Q rising

  Data Path: u2/rcnt_30 to u2/state_FFd3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              3   0.720   1.246  u2/rcnt_30 (u2/rcnt_30)
     LUT4:I0->O            1   0.551   0.827  u2/Ker6129 (CHOICE98)
     LUT4:I3->O            1   0.551   0.869  u2/Ker6133 (CHOICE99)
     LUT4:I2->O            9   0.551   1.192  u2/Ker6159 (u2/N6)
     LUT4_D:I2->O          2   0.551   0.945  u2/_n0007 (u2/_n0007)
     LUT3_L:I2->LO         1   0.551   0.000  u2/state_FFd3-In_G (N549)
     MUXF5:I1->O           1   0.360   0.000  u2/state_FFd3-In (u2/state_FFd3-In)
     FDC:D                     0.203          u2/state_FFd3
    ----------------------------------------
    Total                      9.117ns (4.038ns logic, 5.079ns route)
                                       (44.3% logic, 55.7% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'u1/bclk:Q'
  Total number of paths / destination ports: 153 / 142
-------------------------------------------------------------------------
Offset:              6.289ns (Levels of Logic = 3)
  Source:            reset (PAD)
  Destination:       u2/rbufs_6 (FF)
  Destination Clock: u1/bclk:Q rising

  Data Path: reset to u2/rbufs_6
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            51   0.821   1.988  reset_IBUF (reset_IBUF)
     LUT4_D:I3->O          3   0.551   0.975  u2/Ker81_SW6 (N536)
     LUT4:I2->O            1   0.551   0.801  u2/_n00141 (u2/_n0014)
     FDE:CE                    0.602          u2/rbufs_6
    ----------------------------------------
    Total                      6.289ns (2.525ns logic, 3.764ns route)
                                       (40.1% logic, 59.9% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'u1/bclk:Q'
  Total number of paths / destination ports: 11 / 11
-------------------------------------------------------------------------
Offset:              7.241ns (Levels of Logic = 1)
  Source:            u2/r_ready (FF)
  Destination:       rec_ready (PAD)
  Source Clock:      u1/bclk:Q rising

  Data Path: u2/r_ready to rec_ready
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              2   0.720   0.877  u2/r_ready (u2/r_ready)
     OBUF:I->O                 5.644          rec_ready_OBUF (rec_ready)
    ----------------------------------------
    Total                      7.241ns (6.364ns logic, 0.877ns route)
                                       (87.9% logic, 12.1% route)

=========================================================================
CPU : 9.14 / 9.47 s | Elapsed : 9.00 / 9.00 s
 
--> 

Total memory usage is 102976 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    4 (   0 filtered)
Number of infos    :    1 (   0 filtered)