top.syr

一种实现计算机接口rs232与FPGA通信的基于VHDL语言设计的一段非常简洁的程序

Release 7.1.04i - xst H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
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--> Parameter xsthdpdir set to ./xst
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--> Reading design: top.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "top.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "top"
Output Format                      : NGC
Target Device                      : xc3s400-4-pq208

---- Source Options
Top Module Name                    : top
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : top.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes
enable_auto_floorplanning          : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "F:/data file/uart01/baud.vhd" in Library work.
Architecture behavioral of Entity baud is up to date.
Compiling vhdl file "F:/data file/uart01/reciever.vhd" in Library work.
Architecture behavioral of Entity reciever is up to date.
Compiling vhdl file "F:/data file/uart01/transfer.vhd" in Library work.
Entity <transfer> compiled.
Entity <transfer> (Architecture <behavioral>) compiled.
Compiling vhdl file "F:/data file/uart01/uart.vhd" in Library work.
Entity <top> compiled.
Entity <top> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top> (Architecture <behavioral>).
WARNING:Xst:1542 - "F:/data file/uart01/uart.vhd" line 56: No default binding for component: <reciever>. Generic <framlenr> is not on the component.
WARNING:Xst:1542 - "F:/data file/uart01/uart.vhd" line 58: No default binding for component: <transfer>. Generic <framlent> is not on the component.
Entity <top> analyzed. Unit <top> generated.

Analyzing Entity <baud> (Architecture <behavioral>).
Entity <baud> analyzed. Unit <baud> generated.

Analyzing Entity <reciever> (Architecture <behavioral>).
Entity <reciever> analyzed. Unit <reciever> generated.

Analyzing Entity <transfer> (Architecture <behavioral>).
Entity <transfer> analyzed. Unit <transfer> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <transfer>.
    Related source file is "F:/data file/uart01/transfer.vhd".
WARNING:Xst:1780 - Signal <tcnt> is never used or assigned.
    Found finite state machine <FSM_0> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 5                                              |
    | Transitions        | 11                                             |
    | Inputs             | 4                                              |
    | Outputs            | 5                                              |
    | Clock              | bclkt (rising_edge)                            |
    | Reset              | resett (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | x_idle                                         |
    | Power Up State     | x_idle                                         |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <txd_done>.
    Found 5-bit comparator greatequal for signal <$n0006> created at line 55.
    Found 5-bit comparator greatequal for signal <$n0007> created at line 58.
    Found 5-bit adder for signal <$n0018> created at line 51.
    Found 32-bit adder for signal <$n0019> created at line 65.
    Found 1-bit register for signal <txds>.
    Found 32-bit register for signal <xbitcnt>.
    Found 5-bit register for signal <xcnt16>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  39 D-type flip-flop(s).
	inferred   2 Adder/Subtractor(s).
	inferred   2 Comparator(s).
Unit <transfer> synthesized.


Synthesizing Unit <reciever>.
    Related source file is "F:/data file/uart01/reciever.vhd".
    Found finite state machine <FSM_1> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 5                                              |
    | Transitions        | 10                                             |
    | Inputs             | 4                                              |
    | Outputs            | 5                                              |
    | Clock              | bclkr (rising_edge)                            |
    | Reset              | resetr (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | r_start                                        |
    | Power Up State     | r_start                                        |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 8-bit register for signal <rbuf>.
    Found 1-bit register for signal <r_ready>.
    Found 4-bit comparator greatequal for signal <$n0006> created at line 68.
    Found 4-bit adder for signal <$n0025> created at line 57.
    Found 32-bit adder for signal <$n0026> created at line 75.
    Found 4-bit register for signal <count>.
    Found 8-bit register for signal <rbufs>.
    Found 32-bit register for signal <rcnt>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  53 D-type flip-flop(s).
	inferred   2 Adder/Subtractor(s).
	inferred   1 Comparator(s).
Unit <reciever> synthesized.


Synthesizing Unit <baud>.
    Related source file is "F:/data file/uart01/baud.vhd".
    Found 1-bit register for signal <bclk>.
    Found 32-bit comparator greatequal for signal <$n0002> created at line 41.
    Found 32-bit up counter for signal <cnt>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
	inferred   1 Comparator(s).
Unit <baud> synthesized.


Synthesizing Unit <top>.
    Related source file is "F:/data file/uart01/uart.vhd".
Unit <top> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Analyzing FSM <FSM_1> for best encoding.
Optimizing FSM <FSM_1> on signal <state[1:3]> with sequential encoding.
----------------------
 State    | Encoding
----------------------
 r_start  | 000
 r_center | 001
 r_wait   | 010
 r_sample | 100
 r_stop   | 011
----------------------
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <FSM_0> on signal <state[1:5]> with speed1 encoding.
---------------------
 State   | Encoding
---------------------
 x_idle  | 10000
 x_start | 01000
 x_wait  | 00100
 x_shift | 00001
 x_stop  | 00010
---------------------
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 2
# Adders/Subtractors               : 4
 32-bit adder                      : 2
 4-bit adder                       : 1
 5-bit adder                       : 1
# Counters                         : 1
 32-bit up counter                 : 1
# Registers                        : 25
 1-bit register                    : 20
 32-bit register                   : 2
 4-bit register                    : 1
 5-bit register                    : 1
 8-bit register                    : 1
# Comparators                      : 4
 32-bit comparator greatequal      : 1
 4-bit comparator greatequal       : 1
 5-bit comparator greatequal       : 2