📄 poc_printer.map.talkback.xml

📁 用VHDL语言讲述输出控制器（POC）的设计
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<!--
This XML file (created on Sun Mar 08 23:37:50 2009) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature.  To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder.  For more information, go
to license.txt.
-->
<talkback>
<ver>6.0</ver>
<schema>quartus_version_6.0_build_178.xsd</schema>
<license>
	<host_id>0015c57c3f54</host_id>
	<nic_id>001b777aa91f</nic_id>
	<cdrive_id>5817ba4a</cdrive_id>
</license>
<tool>
	<name>Quartus II</name>
	<version>6.0</version>
	<build>Build 178</build>
	<binary_type>32</binary_type>
	<module>quartus_map</module>
	<edition>Full Version</edition>
	<eval>Licensed</eval>
	<compilation_end_time>Sun Mar 08 23:37:50 2009</compilation_end_time>
</tool>
<machine>
	<os>Unknown</os>
	<cpu>
		<proc_count>2</proc_count>
		<cpu_freq units="MHz">1995</cpu_freq>
	</cpu>
	<ram units="MB">1014</ram>
</machine>
<project>D:/shiy/POC_PRINTER</project>
<revision>POC_PRINTER</revision>
<compilation_summary>
	<flow_status>Flow Failed - Sun Mar 08 23:37:50 2009</flow_status>
	<quartus_ii_version>6.0 Build 178 04/27/2006 SJ Full Version</quartus_ii_version>
	<revision_name>POC_PRINTER</revision_name>
	<top_level_entity_name>PRINTER</top_level_entity_name>
	<family>Stratix</family>
	<met_timing_requirements>N/A</met_timing_requirements>
</compilation_summary>
<mep_data>
	<command_line>quartus_map --read_settings_files=on --write_settings_files=off POC_PRINTER -c POC_PRINTER</command_line>
</mep_data>
<software_data>
	<smart_recompile>off</smart_recompile>
</software_data>
<messages>
	<error>Error: Quartus II Analysis &amp; Synthesis was unsuccessful. 4 errors, 0 warnings</error>
	<error>Error: Elapsed time: 00:00:02</error>
	<error>Error: Processing ended: Sun Mar 08 23:37:50 2009</error>
	<error>Error: Can&apos;t elaborate top-level user hierarchy</error>
	<error>Error (10001): Verilog HDL or VHDL error at PRINTER.vhd(17): couldn&apos;t implement registers for assignments on this clock edge</error>
	<info>Info (10041): Verilog HDL or VHDL info at PRINTER.vhd(13): inferred latch for &quot;RDY&quot;</info>
	<info>Info: Elaborating entity &quot;PRINTER&quot; for the top level hierarchy</info>
	<info>Info: Found 1 design units, including 1 entities, in source file POC_PRINTER.bdf</info>
	<info>Info: Found entity 1: POC_PRINTER</info>
	<info>Info: Found 2 design units, including 1 entities, in source file PRINTER.vhd</info>
</messages>
<analysis___synthesis_settings>
	<row>
		<option>Top-level entity name</option>
		<setting>PRINTER</setting>
		<default_value>POC_PRINTER</default_value>
	</row>
	<row>
		<option>Family name</option>
		<setting>Stratix</setting>
		<default_value>Stratix</default_value>
	</row>
	<row>
		<option>Use smart compilation</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Restructure Multiplexers</option>
		<setting>Auto</setting>
		<default_value>Auto</default_value>
	</row>
	<row>
		<option>Create Debugging Nodes for IP Cores</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Preserve fewer node names</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Disable OpenCore Plus hardware evaluation</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Verilog Version</option>
		<setting>Verilog_2001</setting>
		<default_value>Verilog_2001</default_value>
	</row>
	<row>
		<option>VHDL Version</option>
		<setting>VHDL93</setting>
		<default_value>VHDL93</default_value>
	</row>
	<row>
		<option>State Machine Processing</option>
		<setting>Auto</setting>
		<default_value>Auto</default_value>
	</row>
	<row>
		<option>Extract Verilog State Machines</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Extract VHDL State Machines</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Add Pass-Through Logic to Inferred RAMs</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>DSP Block Balancing</option>
		<setting>Auto</setting>
		<default_value>Auto</default_value>
	</row>
	<row>
		<option>Maximum DSP Block Usage</option>
		<setting>Unlimited</setting>
		<default_value>Unlimited</default_value>
	</row>
	<row>
		<option>NOT Gate Push-Back</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Power-Up Don&apos;t Care</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Remove Redundant Logic Cells</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Remove Duplicate Registers</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Ignore CARRY Buffers</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Ignore CASCADE Buffers</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Ignore GLOBAL Buffers</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Ignore ROW GLOBAL Buffers</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Ignore LCELL Buffers</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Ignore SOFT Buffers</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Limit AHDL Integers to 32 Bits</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Optimization Technique -- Stratix/Stratix GX</option>
		<setting>Balanced</setting>
		<default_value>Balanced</default_value>
	</row>
	<row>
		<option>Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II</option>
		<setting>70</setting>
		<default_value>70</default_value>
	</row>
	<row>
		<option>Auto Carry Chains</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto Open-Drain Pins</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Remove Duplicate Logic</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Perform WYSIWYG Primitive Resynthesis</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Perform gate-level register retiming</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Allow register retiming to trade off Tsu/Tco with Fmax</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto ROM Replacement</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto RAM Replacement</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto DSP Block Replacement</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto Shift Register Replacement</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto Clock Enable Replacement</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Allow Synchronous Control Signals</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Force Use of Synchronous Clear Signals</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Auto RAM Block Balancing</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto Resource Sharing</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Allow Any RAM Size For Recognition</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Allow Any ROM Size For Recognition</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Allow Any Shift Register Size For Recognition</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Maximum Number of M512 Memory Blocks</option>
		<setting>Unlimited</setting>
		<default_value>Unlimited</default_value>
	</row>
	<row>
		<option>Maximum Number of M4K Memory Blocks</option>
		<setting>Unlimited</setting>
		<default_value>Unlimited</default_value>
	</row>
	<row>
		<option>Maximum Number of M-RAM Memory Blocks</option>
		<setting>Unlimited</setting>
		<default_value>Unlimited</default_value>
	</row>
	<row>
		<option>Ignore translate_off and translate_on Synthesis Directives</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Show Parameter Settings Tables in Synthesis Report</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Ignore Maximum Fan-Out Assignments</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Retiming Meta-Stability Register Sequence Length</option>
		<setting>2</setting>
		<default_value>2</default_value>
	</row>
	<row>
		<option>PowerPlay Power Optimization</option>
		<setting>Normal compilation</setting>
		<default_value>Normal compilation</default_value>
	</row>
	<row>
		<option>HDL message level</option>
		<setting>Level2</setting>
		<default_value>Level2</default_value>
	</row>
</analysis___synthesis_settings>
</talkback>
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