frequency.txt

一种等精度的频率计

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity counter is
       Port ( input,khclk12,disclk : in std_logic;
                       sel: OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
                      
                    LED7S : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)); 
        end counter;
architecture B of counter is
signal clr,enk,sellock:std_logic;
signal CQ1:STD_LOGIC_VECTOR(3 DOWNTO 0);
signal CQ2:STD_LOGIC_VECTOR(3 DOWNTO 0);
signal CQ3:STD_LOGIC_VECTOR(3 DOWNTO 0);
signal CQ4:STD_LOGIC_VECTOR(3 DOWNTO 0);
signal CQ5:STD_LOGIC_VECTOR(3 DOWNTO 0);
signal CQ6:STD_LOGIC_VECTOR(3 DOWNTO 0);
signal led_temp: std_logic_vector(3 downto 0);
signal sele: std_logic_vector(2 downto 0);
signal a: std_logic_vector(2 downto 0);
signal b: std_logic_vector(9 downto 0);
signal q1,q2:integer range 1 to 1000;
signal REG1,REG2,REG3,REG4,REG5,REG6:STD_LOGIC_VECTOR(3 DOWNTO 0);




BEGIN

 cnt1000:PROCESS(input, clr, enk)
  VARIABLE  CQg : STD_LOGIC_VECTOR(3 DOWNTO 0);
  VARIABLE  CQs : STD_LOGIC_VECTOR(3 DOWNTO 0); 
  VARIABLE  CQb : STD_LOGIC_VECTOR(3 DOWNTO 0); 
  VARIABLE  CQq : STD_LOGIC_VECTOR(3 DOWNTO 0);
  VARIABLE  CQw : STD_LOGIC_VECTOR(3 DOWNTO 0); 
  VARIABLE  CQy : STD_LOGIC_VECTOR(3 DOWNTO 0); 
 BEGIN
  IF clr = '1' THEN   CQg := (OTHERS =>'0') ; 
                      CQs := (OTHERS =>'0') ;
                      CQb := (OTHERS =>'0') ;
                      CQq := (OTHERS =>'0') ; 
                      CQw := (OTHERS =>'0') ;
                      CQy := (OTHERS =>'0') ;
                            --计数器复位          
     ELSIF input'EVENT AND input='1' THEN      
                            --检测时钟上升沿
IF enk = '1' THEN                     
     IF CQg < "1001" THEN   
     CQg := CQg + 1;     --允许计数  
     ELSE    
     CQg:= (OTHERS =>'0');--大于9，计数值清零
    
     IF CQs < "1001" THEN   
     CQs := CQs + 1;     --允许计数  
     ELSE    
     CQs:= (OTHERS =>'0');--大于9，计数值清零 
     
     IF CQb < "1001" THEN   
     CQb := CQb + 1;     --允许计数  
     ELSE    
     CQb:= (OTHERS =>'0');--大于9，计数值清零 
    IF CQq < "1001" THEN   
     CQq := CQq + 1;     --允许计数  
     ELSE    
     CQq:= (OTHERS =>'0');--大于9，计数值清零 
   IF CQw < "1001" THEN   
     CQw := CQw + 1;     --允许计数  
     ELSE    
     CQw:= (OTHERS =>'0');--大于9，计数值清零 
   IF CQy < "1001" THEN   
     CQy := CQy + 1;     --允许计数  
     ELSE    
     CQy:= (OTHERS =>'0');--大于9，计数值清零 
   end if;
  end if;   
  END IF;
  END IF;
  END IF;
  END IF; 
  END IF;
  END IF;  
   CQ1 <= CQg; 
   CQ2 <= CQs; 
   CQ3 <= CQb;
   CQ4 <= CQq; 
   CQ5 <= CQw; 
   CQ6 <= CQy;  
  
END PROCESS cnt1000;






process(enk,khclk12)
begin
if khclk12='0' AND enk='0' THEN 
  clr<='1';
else clr<='0';
end if;
end process ;

process(khclk12)
      begin
      if(khclk12'event and khclk12='1')then
        sellock<=not sellock;
      end if;
    end process ;

process(disclk)
begin
if(disclk'event and disclk='1')then
       if(sele<"111")then
        sele<=sele+1;
      else
       sele<=(OTHERS =>'0') ;
       end if;
      end if;
  sel<=sele;
    end process ;

process(enk,khclk12)
begin
if (enk'event and enk='0') then

 REG1<=CQ1;
 REG2<=CQ2;
 REG3<=CQ3;
 REG4<=CQ4;
 REG5<=CQ5;
 REG6<=CQ6;
end if;
end process ;


 PROCESS( REG1,REG2,REG3,REG4,REG5,REG6) 
  BEGIN
 if(sele="000") then led_temp<=REG6;
  elsif(sele="001") then led_temp<=REG5;
  elsif(sele="010") then led_temp<=REG4;
  elsif(sele="011") then led_temp<=REG3;
  elsif(sele="100") then led_temp<=REG2;
  elsif(sele="101") then led_temp<=REG1;
  elsif(sele="110") then led_temp<="1111";
  elsif(sele="111") then led_temp<="1101";
  end if;
  CASE  led_temp  IS 
   WHEN "0000" =>  LED7S <= "0111111" ;  
   WHEN "0001" =>  LED7S <= "0000110" ;  
   WHEN "0010" =>  LED7S <= "1011011" ;  
   WHEN "0011" =>  LED7S <= "1001111" ;  
   WHEN "0100" =>  LED7S <= "1100110" ;  
   WHEN "0101" =>  LED7S <= "1101101" ;  
   WHEN "0110" =>  LED7S <= "1111101" ; 
   WHEN "0111" =>  LED7S <= "0000111" ; 
   WHEN "1000" =>  LED7S <= "1111111" ;  
   WHEN "1001" =>  LED7S <= "1101111" ;
   WHEN "1010" =>  LED7S <= "1110111" ;  
   WHEN "1011" =>  LED7S <= "1111100" ;  
   WHEN "1100" =>  LED7S <= "0111001" ; 
   WHEN "1101" =>  LED7S <= "0000000" ; 
   WHEN "1110" =>  LED7S <= "1110111" ;  
   WHEN "1111" =>  LED7S <= "1110110" ;    
   WHEN OTHERS =>  NULL ; 
   END CASE ; 
 end PROCESS ; 

enk<=sellock;       
 END B;