synplify.prd

《设计与验证VerilogHDL》源码实例 和 Verilog规范

#-- Synplicity, Inc.
#-- Version Synplify Pro 8.1
#-- Project file C:\prj\Example-4-10\decode\case\synplify.prd
#-- Written on Fri Jan 13 16:06:50 2006

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### Watch Implementation type ###
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watch_impl -all
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### Watch Implementation properties ###
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watch_prop -clear