rtlc_args1.file

《设计与验证VerilogHDL》源码实例 和 Verilog规范

4:-VLE
6:-mixed
22:-suppress_ver_warnings
11:-driver_pid
15:1364@cceieigjbh
11:-top_module
9:single_if
5:-main
9:single_if
8:-thr_opt
7:-no_drc
8:-fsm_opt
5:-2000
7:-xprobe
10:-infer_rom
11:-xor_eq_opt
11:-flatten_or
1:0
10:-infer_mem
9:precision
12:-one_hot_enc
9:-tech_map
14:-infer_counter
1:2
12:-pri_enc_opt
12:-no_add3_opt
12:-pconst_prop
10:-allow_WFU
10:-allow_FSW
10:-allow_UFO
12:-flatten_and
1:0
10:-force_all
10:-allow_4ST
15:-mux_factor_opt
14:-no_addbuf_opt
10:-pipe_flow
10:-allow_GSD
15:-fast_partition
11:-msgpipefdr
3:196
10:-res_share
12:-vecwriteopt
10:-allow_CVD
10:-allow_FRN
14:-ctrl_mux_flat
5:never
11:-xdbpipefdr
3:160
10:-allow_MDR
13:-use_sync_dff
11:-msgpipefdw
3:324
13:-new_mux_flow
10:-allow_ISL
14:-if_els_if_mod
12:-disable_opt
14:-infer_case_op
1:2
16:-new_mux_costing
11:-xdbpipefdw
3:168
15:-aggressive_rom
16:-fpga_technology
10:lattice_ec
15:-no_cross_share
18:-fsm_opt_thru_hier
13:-disable_incr
15:-implicit_state
3:opt
15:-encoding_style
4:auto
15:-use_enable_dff
19:-ctrl_sub_prog_flat
4:1024
15:-preserve_mults
14:-exemplar_best
16:-new_or_simplify
17:-upper_enum_break
3:800
19:-infer_var_shifters
17:-lower_enum_break
1:5
16:-xilinx_tech_map
19:-generic_shine_thru
14:-disable_dumps
19:-barrel_shifter_opt
18:-res_share_mux_opt
17:-bundle_instances
20:-inline_flatten_proc
14:-exemplar_eval
1:1
19:-bind_mem_instances
18:-mux_anded_sel_opt
22:-gnd_hanging_terminals
20:-enable_time_support
24:-dont_infer_sel_counters
21:-precision_port_style
24:-mux_factor_sel_cone_opt
24:-if_else_if_for_condasgn
19:-aggressive_if2case
17:-acceptance_level
6:medium
19:-preserve_name_case
18:-enable_size_check
20:-enable_case_pragmas
19:-relaxed_mem_checks
21:-hdl_array_name_style
6:%s(%d)
20:-enable_BHV_messages
21:-simple_vecwrite_impl
22:-legalize_module_names
26:-set_evaluated_return_size
29:-retain_bbox_param_value_type
29:-partial_sanity_for_techcells
28:-evaluate_decls_in_generates
24:-dont_traverse_techcells
4:-hdl
7:verilog
2:-v
61:C:/eda/ispTOOLS5_0/precision/pkgs/rtlc_psr/rtlc/lib/dw.rtlc.v
8:-thr_opt
7:-no_drc
8:-fsm_opt
5:-2000
7:-xprobe
10:-infer_rom
11:-xor_eq_opt
11:-flatten_or
1:0
10:-infer_mem
9:precision
12:-one_hot_enc
9:-tech_map
14:-infer_counter
1:2
12:-pri_enc_opt
12:-no_add3_opt
12:-pconst_prop
10:-allow_WFU
10:-allow_FSW
10:-allow_UFO
12:-flatten_and
1:0
10:-force_all
10:-allow_4ST
15:-mux_factor_opt
14:-no_addbuf_opt
10:-pipe_flow
10:-allow_GSD
15:-fast_partition
11:-msgpipefdr
3:196
10:-res_share
12:-vecwriteopt
10:-allow_CVD
10:-allow_FRN
14:-ctrl_mux_flat
5:never
11:-xdbpipefdr
3:160
10:-allow_MDR
13:-use_sync_dff
11:-msgpipefdw
3:324
13:-new_mux_flow
10:-allow_ISL
14:-if_els_if_mod
12:-disable_opt
14:-infer_case_op
1:2
16:-new_mux_costing
11:-xdbpipefdw
3:168
15:-aggressive_rom
16:-fpga_technology
10:lattice_ec
15:-no_cross_share
18:-fsm_opt_thru_hier
13:-disable_incr
15:-implicit_state
3:opt
15:-encoding_style
4:auto
15:-use_enable_dff
19:-ctrl_sub_prog_flat
4:1024
15:-preserve_mults
14:-exemplar_best
16:-new_or_simplify
17:-upper_enum_break
3:800
19:-infer_var_shifters
17:-lower_enum_break
1:5
16:-xilinx_tech_map
19:-generic_shine_thru
14:-disable_dumps
19:-barrel_shifter_opt
18:-res_share_mux_opt
17:-bundle_instances
20:-inline_flatten_proc
14:-exemplar_eval
1:1
19:-bind_mem_instances
18:-mux_anded_sel_opt
22:-gnd_hanging_terminals
20:-enable_time_support
24:-dont_infer_sel_counters
21:-precision_port_style
24:-mux_factor_sel_cone_opt
24:-if_else_if_for_condasgn
19:-aggressive_if2case
17:-acceptance_level
6:medium
19:-preserve_name_case
18:-enable_size_check
20:-enable_case_pragmas
19:-relaxed_mem_checks
21:-hdl_array_name_style
6:%s(%d)
20:-enable_BHV_messages
21:-simple_vecwrite_impl
22:-legalize_module_names
26:-set_evaluated_return_size
29:-retain_bbox_param_value_type
29:-partial_sanity_for_techcells
28:-evaluate_decls_in_generates
24:-dont_traverse_techcells