clk_div_phase.edf

《设计与验证VerilogHDL》源码实例 和 Verilog规范

(edif clk_div_phase
  (edifVersion 2 0 0)
  (edifLevel 0)
  (keywordMap (keywordLevel 0))
  (status
    (written
      (timeStamp 2006 1 11 2 21 19)
      (author "Synplicity, Inc.")
      (program "Synplify Pro" (version "8.1.0, Build 540R"))
     )
   )
  (library VIRTEX
    (edifLevel 0)
    (technology (numberDefinition ))
    (cell IBUF (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port O (direction OUTPUT))
           (port I (direction INPUT))
         )
       )
    )
    (cell OBUF (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port O (direction OUTPUT))
           (port I (direction INPUT))
         )
       )
    )
    (cell LUT3_L (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I0 (direction INPUT))
           (port I1 (direction INPUT))
           (port I2 (direction INPUT))
           (port LO (direction OUTPUT))
         )
       )
    )
    (cell LUT2_L (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I0 (direction INPUT))
           (port I1 (direction INPUT))
           (port LO (direction OUTPUT))
         )
       )
    )
    (cell LUT1_L (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I0 (direction INPUT))
           (port LO (direction OUTPUT))
         )
       )
    )
    (cell BUFGP (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
  )
  (library UNILIB
    (edifLevel 0)
    (technology (numberDefinition ))
    (cell FDP (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port Q (direction OUTPUT))
           (port D (direction INPUT))
           (port C (direction INPUT)
 )
           (port PRE (direction INPUT))
         )
       )
    )
    (cell FDC (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port Q (direction OUTPUT))
           (port D (direction INPUT))
           (port C (direction INPUT)
 )
           (port CLR (direction INPUT))
         )
       )
    )
    (cell INV (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
  )
  (library work
    (edifLevel 0)
    (technology (numberDefinition ))
    (cell clk_div_phase (cellType GENERIC)
       (view verilog (viewType NETLIST)
         (interface
           (port rst (direction INPUT)
 )
           (port clk_200M (direction INPUT)
 )
           (port clk_100M (direction OUTPUT))
           (port clk_50M (direction OUTPUT))
           (port clk_25M (direction OUTPUT))
         )
         (contents
          (instance (rename cnt_0 "cnt[0]") (viewRef PRIM (cellRef FDC (libraryRef UNILIB)))
          )
          (instance (rename cnt_1 "cnt[1]") (viewRef PRIM (cellRef FDC (libraryRef UNILIB)))
          )
          (instance (rename cnt_2 "cnt[2]") (viewRef PRIM (cellRef FDC (libraryRef UNILIB)))
          )
          (instance (rename cnt_rep0_i_0 "cnt_rep0_i[0]") (viewRef PRIM (cellRef FDP (libraryRef UNILIB)))
          )
          (instance (rename cnt_rep0_i_1 "cnt_rep0_i[1]") (viewRef PRIM (cellRef FDP (libraryRef UNILIB)))
          )
          (instance (rename cnt_rep0_i_2 "cnt_rep0_i[2]") (viewRef PRIM (cellRef FDP (libraryRef UNILIB)))
          )
          (instance rst_c_i (viewRef PRIM (cellRef INV (libraryRef UNILIB)))          )
          (instance un3_cnt_axbxc0 (viewRef PRIM (cellRef LUT1_L (libraryRef VIRTEX)))
           (property init (string "1"))
          )
          (instance un3_cnt_axbxc1 (viewRef PRIM (cellRef LUT2_L (libraryRef VIRTEX)))
           (property init (string "6"))
          )
          (instance un3_cnt_axbxc2 (viewRef PRIM (cellRef LUT3_L (libraryRef VIRTEX)))
           (property init (string "78"))
          )
          (instance N_2_i (viewRef PRIM (cellRef LUT2_L (libraryRef VIRTEX)))
           (property init (string "9"))
          )
          (instance N_3_i (viewRef PRIM (cellRef LUT3_L (libraryRef VIRTEX)))
           (property init (string "87"))
          )
          (instance clk_200M_ibuf (viewRef PRIM (cellRef BUFGP (libraryRef VIRTEX)))
          )
          (instance clk_25M_obuf (viewRef PRIM (cellRef OBUF (libraryRef VIRTEX)))
          )
          (instance clk_50M_obuf (viewRef PRIM (cellRef OBUF (libraryRef VIRTEX)))
          )
          (instance clk_100M_obuf (viewRef PRIM (cellRef OBUF (libraryRef VIRTEX)))
          )
          (instance rst_ibuf (viewRef PRIM (cellRef IBUF (libraryRef VIRTEX)))
          )
          (net rst (joined
           (portRef rst)
           (portRef I (instanceRef rst_ibuf))
          ))
          (net (rename clk_200m "clk_200M") (joined
           (portRef clk_200M)
           (portRef I (instanceRef clk_200M_ibuf))
          ))
          (net (rename clk_100m "clk_100M") (joined
           (portRef O (instanceRef clk_100M_obuf))
           (portRef clk_100M)
          ))
          (net (rename clk_50m "clk_50M") (joined
           (portRef O (instanceRef clk_50M_obuf))
           (portRef clk_50M)
          ))
          (net (rename clk_25m "clk_25M") (joined
           (portRef O (instanceRef clk_25M_obuf))
           (portRef clk_25M)
          ))
          (net clk_200M_c (joined
           (portRef O (instanceRef clk_200M_ibuf))
           (portRef C (instanceRef cnt_rep0_i_2))
           (portRef C (instanceRef cnt_rep0_i_1))
           (portRef C (instanceRef cnt_rep0_i_0))
           (portRef C (instanceRef cnt_2))
           (portRef C (instanceRef cnt_1))
           (portRef C (instanceRef cnt_0))
          ))
          (net (rename cntZ0Z_0 "cnt[0]") (joined
           (portRef Q (instanceRef cnt_0))
           (portRef I0 (instanceRef N_3_i))
           (portRef I0 (instanceRef N_2_i))
           (portRef I0 (instanceRef un3_cnt_axbxc2))
           (portRef I0 (instanceRef un3_cnt_axbxc1))
           (portRef I0 (instanceRef un3_cnt_axbxc0))
           (portRef D (instanceRef cnt_rep0_i_0))
          ))
          (net (rename cnt_i_0 "cnt_i[0]") (joined
           (portRef LO (instanceRef un3_cnt_axbxc0))
           (portRef D (instanceRef cnt_0))
          ))
          (net (rename rst_c_iZ0 "rst_c_i") (joined
           (portRef O (instanceRef rst_c_i))
           (portRef PRE (instanceRef cnt_rep0_i_2))
           (portRef PRE (instanceRef cnt_rep0_i_1))
           (portRef PRE (instanceRef cnt_rep0_i_0))
           (portRef CLR (instanceRef cnt_2))
           (portRef CLR (instanceRef cnt_1))
           (portRef CLR (instanceRef cnt_0))
          ))
          (net (rename cntZ0Z_1 "cnt[1]") (joined
           (portRef Q (instanceRef cnt_1))
           (portRef I1 (instanceRef N_3_i))
           (portRef I1 (instanceRef N_2_i))
           (portRef I1 (instanceRef un3_cnt_axbxc2))
           (portRef I1 (instanceRef un3_cnt_axbxc1))
          ))
          (net (rename un3_cnt_axbxcZ0Z1 "un3_cnt_axbxc1") (joined
           (portRef LO (instanceRef un3_cnt_axbxc1))
           (portRef D (instanceRef cnt_1))
          ))
          (net (rename cntZ0Z_2 "cnt[2]") (joined
           (portRef Q (instanceRef cnt_2))
           (portRef I2 (instanceRef N_3_i))
           (portRef I2 (instanceRef un3_cnt_axbxc2))
          ))
          (net (rename un3_cnt_axbxcZ0Z2 "un3_cnt_axbxc2") (joined
           (portRef LO (instanceRef un3_cnt_axbxc2))
           (portRef D (instanceRef cnt_2))
          ))
          (net (rename cnt_rep0_iZ0Z_0 "cnt_rep0_i[0]") (joined
           (portRef Q (instanceRef cnt_rep0_i_0))
           (portRef I (instanceRef clk_100M_obuf))
          ))
          (net (rename cnt_rep0_iZ0Z_1 "cnt_rep0_i[1]") (joined
           (portRef Q (instanceRef cnt_rep0_i_1))
           (portRef I (instanceRef clk_50M_obuf))
          ))
          (net (rename N_2_iZ0 "N_2_i") (joined
           (portRef LO (instanceRef N_2_i))
           (portRef D (instanceRef cnt_rep0_i_1))
          ))
          (net (rename cnt_rep0_iZ0Z_2 "cnt_rep0_i[2]") (joined
           (portRef Q (instanceRef cnt_rep0_i_2))
           (portRef I (instanceRef clk_25M_obuf))
          ))
          (net (rename N_3_iZ0 "N_3_i") (joined
           (portRef LO (instanceRef N_3_i))
           (portRef D (instanceRef cnt_rep0_i_2))
          ))
          (net rst_c (joined
           (portRef O (instanceRef rst_ibuf))
           (portRef I (instanceRef rst_c_i))
          ))
         )
        (property old_syn_reference_clock_1 (string "clk_div_phase|clk_200M,r=0.000000,f=500.000000,u=0.000000,p=1000.000000,clockgroup=Autoconstr_clkgroup_0,rd=0.000000,fd=0.000000,v=0,gen=1"))
       )
    )
  )
  (design clk_div_phase (cellRef clk_div_phase (libraryRef work))
	(property PART (string "xc3s50tq144-4") (owner "Xilinx")))
)