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📁 《设计与验证VerilogHDL》源码实例 和 Verilog规范
💻 SRR
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read_reg_u1.data_out_8[2]       ORCALUT4     Z        Out     1.216     4.553       -         
read_reg_u1.data_out_8[2]       Net          -        -       -         -           1         
read_reg_u1.data_out_2_.Q       FD1P3AX      D        In      0.000     4.553       -         
==============================================================================================


Path information for path number 4: 
    Requested Period:                        0.008
    - Setup time:                            0.324
    = Required time:                         -0.316

    - Propagation time:                      4.553
    = Slack (critical) :                     -4.869

    Number of logic level(s):                2
    Starting point:                          decode_u1.CS_reg2.Q / Q
    Ending point:                            read_reg_u1.data_out_3_.Q / D
    The start point is clocked by            top|CS_ [falling] on pin CK
    The end   point is clocked by            top|OE_ [rising] on pin CK

Instance / Net                               Pin      Pin               Arrival     No. of    
Name                            Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------
decode_u1.CS_reg2.Q             FD1S1A       Q        Out     2.122     2.122       -         
CS_reg2                         Net          -        -       -         -           12        
read_reg_u1.data_out_8_0[3]     ORCALUT4     A        In      0.000     2.122       -         
read_reg_u1.data_out_8_0[3]     ORCALUT4     Z        Out     1.216     3.337       -         
read_reg_u1.data_out_8_0[3]     Net          -        -       -         -           1         
read_reg_u1.data_out_8[3]       ORCALUT4     B        In      0.000     3.337       -         
read_reg_u1.data_out_8[3]       ORCALUT4     Z        Out     1.216     4.553       -         
read_reg_u1.data_out_8[3]       Net          -        -       -         -           1         
read_reg_u1.data_out_3_.Q       FD1P3AX      D        In      0.000     4.553       -         
==============================================================================================


Path information for path number 5: 
    Requested Period:                        0.008
    - Setup time:                            0.324
    = Required time:                         -0.316

    - Propagation time:                      4.553
    = Slack (critical) :                     -4.869

    Number of logic level(s):                2
    Starting point:                          decode_u1.CS_reg2.Q / Q
    Ending point:                            read_reg_u1.data_out_4_.Q / D
    The start point is clocked by            top|CS_ [falling] on pin CK
    The end   point is clocked by            top|OE_ [rising] on pin CK

Instance / Net                               Pin      Pin               Arrival     No. of    
Name                            Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------
decode_u1.CS_reg2.Q             FD1S1A       Q        Out     2.122     2.122       -         
CS_reg2                         Net          -        -       -         -           12        
read_reg_u1.data_out_8_0[4]     ORCALUT4     A        In      0.000     2.122       -         
read_reg_u1.data_out_8_0[4]     ORCALUT4     Z        Out     1.216     3.337       -         
read_reg_u1.data_out_8_0[4]     Net          -        -       -         -           1         
read_reg_u1.data_out_8[4]       ORCALUT4     B        In      0.000     3.337       -         
read_reg_u1.data_out_8[4]       ORCALUT4     Z        Out     1.216     4.553       -         
read_reg_u1.data_out_8[4]       Net          -        -       -         -           1         
read_reg_u1.data_out_4_.Q       FD1P3AX      D        In      0.000     4.553       -         
==============================================================================================




====================================
Detailed Report for Clock: top|OE_
====================================



Starting Points with Worst Slack
********************************

                           Starting                                      Arrival           
Instance                   Reference     Type        Pin     Net         Time        Slack 
                           Clock                                                           
-------------------------------------------------------------------------------------------
write_reg_u1.reg2_0_.Q     top|OE_       FD1P3AX     Q       reg2[0]     1.396       -0.623
write_reg_u1.reg2_1_.Q     top|OE_       FD1P3AX     Q       reg2[1]     1.396       -0.623
write_reg_u1.reg2_2_.Q     top|OE_       FD1P3AX     Q       reg2[2]     1.396       -0.623
write_reg_u1.reg2_3_.Q     top|OE_       FD1P3AX     Q       reg2[3]     1.396       -0.623
write_reg_u1.reg2_4_.Q     top|OE_       FD1P3AX     Q       reg2[4]     1.396       -0.623
write_reg_u1.reg2_5_.Q     top|OE_       FD1P3AX     Q       reg2[5]     1.396       -0.623
write_reg_u1.reg2_6_.Q     top|OE_       FD1P3AX     Q       reg2[6]     1.396       -0.623
write_reg_u1.reg2_7_.Q     top|OE_       FD1P3AX     Q       reg2[7]     1.396       -0.623
write_reg_u1.reg3_0_.Q     top|OE_       FD1P3AX     Q       reg3[0]     1.396       -0.623
write_reg_u1.reg3_1_.Q     top|OE_       FD1P3AX     Q       reg3[1]     1.396       -0.623
===========================================================================================



Worst Path Information
***********************


Path information for path number 1: 
    Requested Period:                        3.528
    - Setup time:                            0.324
    = Required time:                         3.204

    - Propagation time:                      3.827
    = Slack (non-critical) :                 -0.623

    Number of logic level(s):                2
    Starting point:                          write_reg_u1.reg2_0_.Q / Q
    Ending point:                            read_reg_u1.data_out_0_.Q / D
    The start point is clocked by            top|OE_ [rising] on pin CK
    The end   point is clocked by            top|OE_ [rising] on pin CK

Instance / Net                               Pin      Pin               Arrival     No. of    
Name                            Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------
write_reg_u1.reg2_0_.Q          FD1P3AX      Q        Out     1.396     1.396       -         
reg2[0]                         Net          -        -       -         -           1         
read_reg_u1.data_out_8_0[0]     ORCALUT4     B        In      0.000     1.396       -         
read_reg_u1.data_out_8_0[0]     ORCALUT4     Z        Out     1.216     2.611       -         
read_reg_u1.data_out_8_0[0]     Net          -        -       -         -           1         
read_reg_u1.data_out_8[0]       ORCALUT4     B        In      0.000     2.611       -         
read_reg_u1.data_out_8[0]       ORCALUT4     Z        Out     1.216     3.827       -         
read_reg_u1.data_out_8[0]       Net          -        -       -         -           1         
read_reg_u1.data_out_0_.Q       FD1P3AX      D        In      0.000     3.827       -         
==============================================================================================


Path information for path number 2: 
    Requested Period:                        3.528
    - Setup time:                            0.324
    = Required time:                         3.204

    - Propagation time:                      3.827
    = Slack (non-critical) :                 -0.623

    Number of logic level(s):                2
    Starting point:                          write_reg_u1.reg2_1_.Q / Q
    Ending point:                            read_reg_u1.data_out_1_.Q / D
    The start point is clocked by            top|OE_ [rising] on pin CK
    The end   point is clocked by            top|OE_ [rising] on pin CK

Instance / Net                               Pin      Pin               Arrival     No. of    
Name                            Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------
write_reg_u1.reg2_1_.Q          FD1P3AX      Q        Out     1.396     1.396       -         
reg2[1]                         Net          -        -       -         -           1         
read_reg_u1.data_out_8_0[1]     ORCALUT4     B        In      0.000     1.396       -         
read_reg_u1.data_out_8_0[1]     ORCALUT4     Z        Out     1.216     2.611       -         
read_reg_u1.data_out_8_0[1]     Net          -        -       -         -           1         
read_reg_u1.data_out_8[1]       ORCALUT4     B        In      0.000     2.611       -         
read_reg_u1.data_out_8[1]       ORCALUT4     Z        Out     1.216     3.827       -         
read_reg_u1.data_out_8[1]       Net          -        -       -         -           1         
read_reg_u1.data_out_1_.Q       FD1P3AX      D        In      0.000     3.827       -         
==============================================================================================


Path information for path number 3: 
    Requested Period:                        3.528
    - Setup time:                            0.324
    = Required time:                         3.204

    - Propagation time:                      3.827
    = Slack (non-critical) :                 -0.623

    Number of logic level(s):                2
    Starting point:                          write_reg_u1.reg2_2_.Q / Q
    Ending point:                            read_reg_u1.data_out_2_.Q / D
    The start point is clocked by            top|OE_ [rising] on pin CK
    The end   point is clocked by            top|OE_ [rising] on pin CK

Instance / Net                               Pin      Pin               Arrival     No. of    
Name                            Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------
write_reg_u1.reg2_2_.Q          FD1P3AX      Q        Out     1.396     1.396       -         
reg2[2]                         Net          -        -       -         -           1         
read_reg_u1.data_out_8_0[2]     ORCALUT4     B        In      0.000     1.396       -         
read_reg_u1.data_out_8_0[2]     ORCALUT4     Z        Out     1.216     2.611       -         
read_reg_u1.data_out_8_0[2]     Net          -        -       -         -           1         
read_reg_u1.data_out_8[2]       ORCALUT4     B        In      0.000     2.611       -         
read_reg_u1.data_out_8[2]       ORCALUT4     Z        Out     1.216     3.827       -         
read_reg_u1.data_out_8[2]       Net          -        -       -         -           1         
read_reg_u1.data_out_2_.Q       FD1P3AX      D        In      0.000     3.827       -         
==============================================================================================


Path information for path number 4: 
    Requested Period:                        3.528
    - Setup time:                            0.324
    = Required time:                         3.204

    - Propagation time:                      3.827
    = Slack (non-critical) :                 -0.623

    Number of logic level(s):                2
    Starting point:                          write_reg_u1.reg2_3_.Q / Q
    Ending point:                            read_reg_u1.data_out_3_.Q / D
    The start point is clocked by            top|OE_ [rising] on pin CK
    The end   point is clocked by            top|OE_ [rising] on pin CK

Instance / Net                               Pin      Pin               Arrival     No. of    
Name                            Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------
write_reg_u1.reg2_3_.Q          FD1P3AX      Q        Out     1.396     1.396       -         
reg2[3]                         Net          -        -       -         -           1         
read_reg_u1.data_out_8_0[3]     ORCALUT4     B        In      0.000     1.396       -         
read_reg_u1.data_out_8_0[3]     ORCALUT4     Z        Out     1.216     2.611       -         
read_reg_u1.data_out_8_0[3]     Net          -        -       -         -           1         
read_reg_u1.data_out_8[3]       ORCALUT4     B        In      0.000     2.611       -         
read_reg_u1.data_out_8[3]       ORCALUT4     Z        Out     1.216     3.827       -         
read_reg_u1.data_out_8[3]       Net          -        -       -         -           1         
read_reg_u1.data_out_3_.Q       FD1P3AX      D        In      0.000     3.827       -         
==============================================================================================


Path information for path number 5: 
    Requested Period:                        3.528
    - Setup time:                            0.324
    = Required time:                         3.204

    - Propagation time:                      3.827
    = Slack (non-critical) :                 -0.623

    Number of logic level(s):                2
    Starting point:                          write_reg_u1.reg2_4_.Q / Q
    Ending point:                            read_reg_u1.data_out_4_.Q / D
    The start point is clocked by            top|OE_ [rising] on pin CK
    The end   point is clocked by            top|OE_ [rising] on pin CK

Instance / Net                               Pin      Pin               Arrival     No. of    
Name                            Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------
write_reg_u1.reg2_4_.Q          FD1P3AX      Q        Out     1.396     1.396       -         
reg2[4]                         Net          -        -       -         -           1         
read_reg_u1.data_out_8_0[4]     ORCALUT4     B        In      0.000     1.396       -         
read_reg_u1.data_out_8_0[4]     ORCALUT4     Z        Out     1.216     2.611       -         
read_reg_u1.data_out_8_0[4]     Net          -        -       -         -           1         
read_reg_u1.data_out_8[4]       ORCALUT4     B        In      0.000     2.611       -         
read_reg_u1.data_out_8[4]       ORCALUT4     Z        Out     1.216     3.827       -         
read_reg_u1.data_out_8[4]       Net          -        -       -         -           1         
read_reg_u1.data_out_4_.Q       FD1P3AX      D        In      0.000     3.827       -         
==============================================================================================



##### END OF TIMING REPORT #####]

Mapper successful!
Process took 0h:0m:2s realtime, 0h:0m:2s cputime
###########################################################]

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