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📄 decode.srr

📁 《设计与验证VerilogHDL》源码实例 和 Verilog规范
💻 SRR
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Ending Points with Worst Slack
******************************

                              Starting                                                       Required           
Instance                      Reference     Type       Pin     Net                           Time         Slack 
                              Clock                                                                             
----------------------------------------------------------------------------------------------------------------
read_reg_u1.data_out_0_.Q     top|CS_       FD1S1A     D       read_reg_u1.data_out_1[0]     3.284        -0.637
read_reg_u1.data_out_1_.Q     top|CS_       FD1S1A     D       read_reg_u1.data_out_1[1]     3.284        -0.599
read_reg_u1.data_out_2_.Q     top|CS_       FD1S1A     D       read_reg_u1.data_out_1[2]     3.284        -0.599
read_reg_u1.data_out_3_.Q     top|CS_       FD1S1A     D       read_reg_u1.data_out_1[3]     3.284        -0.599
read_reg_u1.data_out_4_.Q     top|CS_       FD1S1A     D       read_reg_u1.data_out_1[4]     3.284        -0.599
read_reg_u1.data_out_5_.Q     top|CS_       FD1S1A     D       read_reg_u1.data_out_1[5]     3.284        -0.599
read_reg_u1.data_out_6_.Q     top|CS_       FD1S1A     D       read_reg_u1.data_out_1[6]     3.284        -0.599
read_reg_u1.data_out_7_.Q     top|CS_       FD1S1A     D       read_reg_u1.data_out_1[7]     3.284        -0.599
decode_u1.CS_reg1.Q           top|CS_       FD1S1A     D       decode_u1.CS_reg1_1           3.284        -0.091
decode_u1.CS_reg2.Q           top|CS_       FD1S1A     D       decode_u1.CS_reg2_1           3.284        -0.053
================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
    Requested Period:                        3.608
    - Setup time:                            0.324
    = Required time:                         3.284

    - Propagation time:                      3.921
    = Slack (critical) :                     -0.637

    Number of logic level(s):                2
    Starting point:                          decode_u1.CS_reg1.Q / Q
    Ending point:                            read_reg_u1.data_out_0_.Q / D
    The start point is clocked by            top|CS_ [falling] on pin CK
    The end   point is clocked by            top|CS_ [falling] on pin CK

Instance / Net                                Pin      Pin               Arrival     No. of    
Name                             Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------
decode_u1.CS_reg1.Q              FD1S1A       Q        Out     2.159     2.159       -         
CS_reg1                          Net          -        -       -         -           14        
read_reg_u1.data_out_1_x0[0]     ORCALUT4     A        In      0.000     2.159       -         
read_reg_u1.data_out_1_x0[0]     ORCALUT4     Z        Out     1.216     3.375       -         
read_reg_u1.data_out_1_x0[0]     Net          -        -       -         -           1         
read_reg_u1.data_out_1[0]        PFUMX        BLUT     In      0.000     3.375       -         
read_reg_u1.data_out_1[0]        PFUMX        Z        Out     0.546     3.921       -         
read_reg_u1.data_out_1[0]        Net          -        -       -         -           1         
read_reg_u1.data_out_0_.Q        FD1S1A       D        In      0.000     3.921       -         
===============================================================================================


Path information for path number 2: 
    Requested Period:                        3.608
    - Setup time:                            0.324
    = Required time:                         3.284

    - Propagation time:                      3.921
    = Slack (critical) :                     -0.637

    Number of logic level(s):                2
    Starting point:                          decode_u1.CS_reg1.Q / Q
    Ending point:                            read_reg_u1.data_out_0_.Q / D
    The start point is clocked by            top|CS_ [falling] on pin CK
    The end   point is clocked by            top|CS_ [falling] on pin CK

Instance / Net                                Pin      Pin               Arrival     No. of    
Name                             Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------
decode_u1.CS_reg1.Q              FD1S1A       Q        Out     2.159     2.159       -         
CS_reg1                          Net          -        -       -         -           14        
read_reg_u1.data_out_1_x1[0]     ORCALUT4     A        In      0.000     2.159       -         
read_reg_u1.data_out_1_x1[0]     ORCALUT4     Z        Out     1.216     3.375       -         
read_reg_u1.data_out_1_x1[0]     Net          -        -       -         -           1         
read_reg_u1.data_out_1[0]        PFUMX        ALUT     In      0.000     3.375       -         
read_reg_u1.data_out_1[0]        PFUMX        Z        Out     0.546     3.921       -         
read_reg_u1.data_out_1[0]        Net          -        -       -         -           1         
read_reg_u1.data_out_0_.Q        FD1S1A       D        In      0.000     3.921       -         
===============================================================================================


Path information for path number 3: 
    Requested Period:                        3.608
    - Setup time:                            0.324
    = Required time:                         3.284

    - Propagation time:                      3.883
    = Slack (non-critical) :                 -0.599

    Number of logic level(s):                2
    Starting point:                          decode_u1.CS_reg2.Q / Q
    Ending point:                            read_reg_u1.data_out_1_.Q / D
    The start point is clocked by            top|CS_ [falling] on pin CK
    The end   point is clocked by            top|CS_ [falling] on pin CK

Instance / Net                                Pin      Pin               Arrival     No. of    
Name                             Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------
decode_u1.CS_reg2.Q              FD1S1A       Q        Out     2.122     2.122       -         
CS_reg2                          Net          -        -       -         -           12        
read_reg_u1.data_out_1_x0[1]     ORCALUT4     A        In      0.000     2.122       -         
read_reg_u1.data_out_1_x0[1]     ORCALUT4     Z        Out     1.216     3.337       -         
read_reg_u1.data_out_1_x0[1]     Net          -        -       -         -           1         
read_reg_u1.data_out_1[1]        PFUMX        BLUT     In      0.000     3.337       -         
read_reg_u1.data_out_1[1]        PFUMX        Z        Out     0.546     3.883       -         
read_reg_u1.data_out_1[1]        Net          -        -       -         -           1         
read_reg_u1.data_out_1_.Q        FD1S1A       D        In      0.000     3.883       -         
===============================================================================================


Path information for path number 4: 
    Requested Period:                        3.608
    - Setup time:                            0.324
    = Required time:                         3.284

    - Propagation time:                      3.883
    = Slack (non-critical) :                 -0.599

    Number of logic level(s):                2
    Starting point:                          decode_u1.CS_reg2.Q / Q
    Ending point:                            read_reg_u1.data_out_2_.Q / D
    The start point is clocked by            top|CS_ [falling] on pin CK
    The end   point is clocked by            top|CS_ [falling] on pin CK

Instance / Net                                Pin      Pin               Arrival     No. of    
Name                             Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------
decode_u1.CS_reg2.Q              FD1S1A       Q        Out     2.122     2.122       -         
CS_reg2                          Net          -        -       -         -           12        
read_reg_u1.data_out_1_x0[2]     ORCALUT4     A        In      0.000     2.122       -         
read_reg_u1.data_out_1_x0[2]     ORCALUT4     Z        Out     1.216     3.337       -         
read_reg_u1.data_out_1_x0[2]     Net          -        -       -         -           1         
read_reg_u1.data_out_1[2]        PFUMX        BLUT     In      0.000     3.337       -         
read_reg_u1.data_out_1[2]        PFUMX        Z        Out     0.546     3.883       -         
read_reg_u1.data_out_1[2]        Net          -        -       -         -           1         
read_reg_u1.data_out_2_.Q        FD1S1A       D        In      0.000     3.883       -         
===============================================================================================


Path information for path number 5: 
    Requested Period:                        3.608
    - Setup time:                            0.324
    = Required time:                         3.284

    - Propagation time:                      3.883
    = Slack (non-critical) :                 -0.599

    Number of logic level(s):                2
    Starting point:                          decode_u1.CS_reg2.Q / Q
    Ending point:                            read_reg_u1.data_out_3_.Q / D
    The start point is clocked by            top|CS_ [falling] on pin CK
    The end   point is clocked by            top|CS_ [falling] on pin CK

Instance / Net                                Pin      Pin               Arrival     No. of    
Name                             Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------
decode_u1.CS_reg2.Q              FD1S1A       Q        Out     2.122     2.122       -         
CS_reg2                          Net          -        -       -         -           12        
read_reg_u1.data_out_1_x0[3]     ORCALUT4     A        In      0.000     2.122       -         
read_reg_u1.data_out_1_x0[3]     ORCALUT4     Z        Out     1.216     3.337       -         
read_reg_u1.data_out_1_x0[3]     Net          -        -       -         -           1         
read_reg_u1.data_out_1[3]        PFUMX        BLUT     In      0.000     3.337       -         
read_reg_u1.data_out_1[3]        PFUMX        Z        Out     0.546     3.883       -         
read_reg_u1.data_out_1[3]        Net          -        -       -         -           1         
read_reg_u1.data_out_3_.Q        FD1S1A       D        In      0.000     3.883       -         
===============================================================================================



##### END OF TIMING REPORT #####]

Mapper successful!
Process took 0h:0m:1s realtime, 0h:0m:1s cputime
###########################################################]

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