top377

3955步进电机的驱动的cpld的verilog程序,经过测试,可以在ISPLEVER下调试,包括总线的译码等.非常完整

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//
//    3955寄存器 ----0xd000
//                       Bit0: U5_3955_D0
//                       Bit1: U5_3955_D1
//                       Bit2: U5_3955_D2
//                       Bit3: U5_PHASE1
//                       Bit4: U15_3955_D0
//                       Bit5: U15_3955_D1
//                       Bit6: U15_3955_D2
//                       Bit7: U15_PHASE2
//
//   



//    按键输入    ---0xf000


module Top(CPLD_CLK, SD, AHI, ALE, RD, WR,      
          BMOD,BSTAT,AMOD,ASTAT,                                             //互联口定义
          CL_KEY, RW_KEY,
          POINT5V, POINT12V,
          DISP_CS, DISP_RES, DISP_DC,            
          SDD, RD_CPLD, WR_CPLD,
          U5_3955_D0, U5_3955_D1, U5_3955_D2, U5_PHASE1,
          U15_3955_D0, U15_3955_D1, U15_3955_D2, U15_PHASE2,
          LED1, LED2, LED3, LED4,LED6, USB_CS,INT0_CPLD,ADDROUT,
	  AD_OUT,AD_DI,AD_CLOCK,AD_CS,EOC,PLACE,MOTORLOOP,
          SPEAKER,CLK2,INT0,INT1,); 
         

reg 	speaker_tone1,speaker_tone2,speaker_tone3;//speaker_tone4;
reg     [2:0] SPVOL_reg = 3'b000;      //音量选择

output  INT0,INT1,USB_CS,ADDROUT;   
input   INT0_CPLD;
input   EOC;
assign  INT0=INT0_CPLD;


input		CPLD_CLK;
input		CLK2;                  //专用于声音的14.4kHz的音频
inout	[7:0]	SD;                    //双向数据总线
input	[15:8]	AHI;                   //地址高8位
reg     [15:8]  AHI_reg;
reg	[7:0]	alow;                  //低8位地址码寄存器

input		ALE;                   //地址锁存信号
input		RD;                    //cpu读信号输入
input		WR;		       //cpu写信号输入
inout	[7:0]	SDD;
output		RD_CPLD;
output		WR_CPLD;
reg	[7:0]	SD_tmp;                //
reg     [15:0]  count16; 
reg	       AD_CLOCK_reg,AD_CS_reg,AD_DI_reg;
input          AD_OUT;                     //AD_OUT作为CPLD的输入口
input          PLACE; 
input	       MOTORLOOP;


//assign          INT0=1;

//---------------------下面为对应的进程程序---------------------------------


//********************ALE下降沿时锁存低7位地址值*****************
always @(negedge ALE) begin         
    alow[7:0] <=  SD;
    AHI_reg[15:8] <=  AHI[15:8] ;
end


//*************************  组合状态 及更新 *************************
reg [7:0] state;                      //外设的状态
reg [7:0] AEO;              //输入另机的状态和模式的组合  地址：0x8001






//***********OLED的定义****************************************
output		DISP_CS, DISP_RES, DISP_DC;    //OLED的控制信号,其他在总线

//***************总线的读写逻辑****************
assign SDD = ((WR==1'b0)&&((DISP_CS==1'b0)||(USB_CS==1'b0))) ? SD: 8'bzzzzzzzz;    //这是连续赋值语句，如果AHI_reg==8'b10100000时，将SDD连到SD，否则SDD为高阻
//assign SD  =  ((WR==1'b1)&&((DISP_CS==1'b0)||(USB_CS==1'b0)))  ? SDD:SD_tmp ;
assign SD  = (RD==1'b0) ? SD_tmp : 8'bzzzzzzzz;    //在编码为A0、C0时的sdd已经指向了sd，所以这句就不要了
assign RD_CPLD = RD;                               //RD、WR的直通赋值
assign WR_CPLD = WR;


//OLED的读
assign DISP_CS  = ! (AHI_reg[15:8] == 8'b10100000);       //A0开始
assign DISP_DC  = ({AHI_reg, alow} == 16'ha001);          //数据口A001    //命令口A002
assign DISP_RES = !({AHI_reg, alow} == 16'ha003);         //复位A003
//USB的读

assign  USB_CS  =  ! (AHI_reg[15:8] == 8'b11000000);       //C0开始
assign  ADDROUT = (USB_CS==1'b0)? alow[0]:1'bz;                                 //({AHI_reg, alow} == 16'hc001) ? 1'b1:1'b0; //ADDROUT实际与A0相连

//***********************对总线的直通处理,读数据时必须 *******************************
//reg   ADDROUT_reg;  //USB_CS_reg,
//assign USB_CS =USB_CS_reg;
//assign ADDROUT=ADDROUT_reg;

always @(AHI_reg or alow)
begin
    case ({AHI_reg, alow})
        16'ha000: SD_tmp = SDD;                               //
        16'ha001: SD_tmp = SDD;
        16'ha002: SD_tmp = SDD;
        16'ha003: SD_tmp = SDD;                               
        16'hc000:             //CH372的数据口
//                  begin  
//                   if (RD==1'b0)
                    SD_tmp = SDD;
//                  end  
        16'hc001:                   //CH372的命令口
//                   begin  
//                    if (RD==1'b0)
                    SD_tmp = SDD;
//                     end                   
  
//      case ({AHI_reg, alow})
        16'he000: SD_tmp = state;
        16'h8001: SD_tmp = AEO;                           //读出另机状态
        16'he003: SD_tmp = MOTORLOOP_LAB;
        16'hf000: SD_tmp = key[7:0];    //今后不管是否数字键，所有的键盘值都采用编码值 
 //       default   begin
     //             USB_CS_reg  = 1'b1; 
  //                ADDROUT_reg = 1'bz;
  //                end  
    endcase
end


//**********步进电机的定义************************************
output		U5_3955_D0, U5_3955_D1, U5_3955_D2, U5_PHASE1;
reg		U5_3955_D0_reg, U5_3955_D1_reg, U5_3955_D2_reg, U5_PHASE1_reg;
assign          U5_3955_D0 = U5_3955_D0_reg;
assign          U5_3955_D1 = U5_3955_D1_reg;
assign          U5_3955_D2 = U5_3955_D2_reg;
assign          U5_PHASE1  = U5_PHASE1_reg;

output		U15_3955_D0, U15_3955_D1, U15_3955_D2, U15_PHASE2;
reg		U15_3955_D0_reg, U15_3955_D1_reg, U15_3955_D2_reg, U15_PHASE2_reg;
assign          U15_3955_D0=U15_3955_D0_reg;
assign          U15_3955_D1=U15_3955_D1_reg;

assign          U15_3955_D2=U15_3955_D2_reg;
assign          U15_PHASE2=U15_PHASE2_reg;


//**********发光二极管的定义*********************************
output		LED1, LED2, LED3, LED4,LED6;
reg		LED1_reg, LED2_reg, LED3_reg, LED4_reg,LED6_reg;
assign          LED1=~LED1_reg;
assign          LED2=~LED2_reg;
assign          LED3=LED3_reg;
assign          LED4=LED4_reg;
assign          LED6=~LED6_reg;

//************输入与输出的定义**********************************************

output	        AD_CLOCK,AD_DI, AD_CS,  SPEAKER;        //已将AD的DI和DO分开，DI在140脚  
assign 		AD_CLOCK=AD_CLOCK_reg;
assign 		AD_DI=AD_DI_reg;
assign 		AD_CS	=AD_CS_reg; 
input		POINT5V, POINT12V;






//************************LABEL分频***************************
reg label;

always @(posedge CPLD_CLK)    //分频
       begin
     		if (count16 == 16'b1111111111111110)
          	   begin
                    count16 <= 16'b0000000000000000;    //计数100就清0
                    label <= ~label;
		   end
                 else
                     count16 <= #1 count16 + 1;
end









//******步进电机的译码***************************
reg step_wr_enable;

always @(AHI_reg,alow) 
 begin         //ALE下降沿时锁存低7位地址值
   if ({AHI_reg, alow} == 16'hd000 ) 
       step_wr_enable <= WR ;
   else step_wr_enable<= 1'b1;
  end

always @(posedge step_wr_enable) 
        begin
                  U5_3955_D0_reg  <=  SD[0];
                  U5_3955_D1_reg  <=  SD[1];
                  U5_3955_D2_reg  <=  SD[2];
                  U5_PHASE1_reg   <=  SD[3];
                  U15_3955_D0_reg <=  SD[4];
                  U15_3955_D1_reg <=  SD[5];
                  U15_3955_D2_reg <=  SD[6];
                  U15_PHASE2_reg  <=  SD[7];
        end

//    开关量输出：       
//                0XE006:AD_CLOCK    这是阻塞的时钟输出的允许位，
// 			 时钟始终是存在的向该位输出1，则ENABLE
//                0XE007:AD_CS
//                0xe009:SPEAKER      报警喇叭



endmodule