sysfenpin.tan.qmsg

用VHDL语言编写的8*8点阵显示“北京08”的程序。可以用FPGA实现。可将程序当中的“北京08”改成别的汉字显示。

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register tout2\[5\] register tout2\[10\] 241.95 MHz 4.133 ns Internal " "Info: Clock \"clk\" has Internal fmax of 241.95 MHz between source register \"tout2\[5\]\" and destination register \"tout2\[10\]\" (period= 4.133 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.872 ns + Longest register register " "Info: + Longest register to register delay is 3.872 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns tout2\[5\] 1 REG LC_X2_Y12_N8 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y12_N8; Fanout = 5; REG Node = 'tout2\[5\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { tout2[5] } "NODE_NAME" } } { "sysfenpin.vhd" "" { Text "C:/Documents and Settings/user/桌面/各个分模块/sysfenpin/sysfenpin.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.171 ns) + CELL(0.590 ns) 1.761 ns Equal1~102 2 COMB LC_X2_Y13_N1 1 " "Info: 2: + IC(1.171 ns) + CELL(0.590 ns) = 1.761 ns; Loc. = LC_X2_Y13_N1; Fanout = 1; COMB Node = 'Equal1~102'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.761 ns" { tout2[5] Equal1~102 } "NODE_NAME" } } { "sysfenpin.vhd" "" { Text "C:/Documents and Settings/user/桌面/各个分模块/sysfenpin/sysfenpin.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 2.057 ns Equal1~103 3 COMB LC_X2_Y13_N2 6 " "Info: 3: + IC(0.182 ns) + CELL(0.114 ns) = 2.057 ns; Loc. = LC_X2_Y13_N2; Fanout = 6; COMB Node = 'Equal1~103'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.296 ns" { Equal1~102 Equal1~103 } "NODE_NAME" } } { "sysfenpin.vhd" "" { Text "C:/Documents and Settings/user/桌面/各个分模块/sysfenpin/sysfenpin.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.208 ns) + CELL(0.607 ns) 3.872 ns tout2\[10\] 4 REG LC_X2_Y12_N6 3 " "Info: 4: + IC(1.208 ns) + CELL(0.607 ns) = 3.872 ns; Loc. = LC_X2_Y12_N6; Fanout = 3; REG Node = 'tout2\[10\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.815 ns" { Equal1~103 tout2[10] } "NODE_NAME" } } { "sysfenpin.vhd" "" { Text "C:/Documents and Settings/user/桌面/各个分模块/sysfenpin/sysfenpin.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.311 ns ( 33.86 % ) " "Info: Total cell delay = 1.311 ns ( 33.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.561 ns ( 66.14 % ) " "Info: Total interconnect delay = 2.561 ns ( 66.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.872 ns" { tout2[5] Equal1~102 Equal1~103 tout2[10] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.872 ns" { tout2[5] Equal1~102 Equal1~103 tout2[10] } { 0.000ns 1.171ns 0.182ns 1.208ns } { 0.000ns 0.590ns 0.114ns 0.607ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.008 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 8.008 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 12 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 12; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "sysfenpin.vhd" "" { Text "C:/Documents and Settings/user/桌面/各个分模块/sysfenpin/sysfenpin.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.935 ns) 2.954 ns cplk~reg0 2 REG LC_X5_Y2_N2 13 " "Info: 2: + IC(0.550 ns) + CELL(0.935 ns) = 2.954 ns; Loc. = LC_X5_Y2_N2; Fanout = 13; REG Node = 'cplk~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.485 ns" { clk cplk~reg0 } "NODE_NAME" } } { "sysfenpin.vhd" "" { Text "C:/Documents and Settings/user/桌面/各个分模块/sysfenpin/sysfenpin.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.343 ns) + CELL(0.711 ns) 8.008 ns tout2\[10\] 3 REG LC_X2_Y12_N6 3 " "Info: 3: + IC(4.343 ns) + CELL(0.711 ns) = 8.008 ns; Loc. = LC_X2_Y12_N6; Fanout = 3; REG Node = 'tout2\[10\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.054 ns" { cplk~reg0 tout2[10] } "NODE_NAME" } } { "sysfenpin.vhd" "" { Text "C:/Documents and Settings/user/桌面/各个分模块/sysfenpin/sysfenpin.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 38.90 % ) " "Info: Total cell delay = 3.115 ns ( 38.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.893 ns ( 61.10 % ) " "Info: Total interconnect delay = 4.893 ns ( 61.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.008 ns" { clk cplk~reg0 tout2[10] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "8.008 ns" { clk clk~out0 cplk~reg0 tout2[10] } { 0.000ns 0.000ns 0.550ns 4.343ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.008 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 8.008 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 12 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 12; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "sysfenpin.vhd" "" { Text "C:/Documents and Settings/user/桌面/各个分模块/sysfenpin/sysfenpin.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.935 ns) 2.954 ns cplk~reg0 2 REG LC_X5_Y2_N2 13 " "Info: 2: + IC(0.550 ns) + CELL(0.935 ns) = 2.954 ns; Loc. = LC_X5_Y2_N2; Fanout = 13; REG Node = 'cplk~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.485 ns" { clk cplk~reg0 } "NODE_NAME" } } { "sysfenpin.vhd" "" { Text "C:/Documents and Settings/user/桌面/各个分模块/sysfenpin/sysfenpin.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.343 ns) + CELL(0.711 ns) 8.008 ns tout2\[5\] 3 REG LC_X2_Y12_N8 5 " "Info: 3: + IC(4.343 ns) + CELL(0.711 ns) = 8.008 ns; Loc. = LC_X2_Y12_N8; Fanout = 5; REG Node = 'tout2\[5\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.054 ns" { cplk~reg0 tout2[5] } "NODE_NAME" } } { "sysfenpin.vhd" "" { Text "C:/Documents and Settings/user/桌面/各个分模块/sysfenpin/sysfenpin.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 38.90 % ) " "Info: Total cell delay = 3.115 ns ( 38.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.893 ns ( 61.10 % ) " "Info: Total interconnect delay = 4.893 ns ( 61.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.008 ns" { clk cplk~reg0 tout2[5] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "8.008 ns" { clk clk~out0 cplk~reg0 tout2[5] } { 0.000ns 0.000ns 0.550ns 4.343ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.008 ns" { clk cplk~reg0 tout2[10] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "8.008 ns" { clk clk~out0 cplk~reg0 tout2[10] } { 0.000ns 0.000ns 0.550ns 4.343ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.008 ns" { clk cplk~reg0 tout2[5] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "8.008 ns" { clk clk~out0 cplk~reg0 tout2[5] } { 0.000ns 0.000ns 0.550ns 4.343ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "sysfenpin.vhd" "" { Text "C:/Documents and Settings/user/桌面/各个分模块/sysfenpin/sysfenpin.vhd" 29 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "sysfenpin.vhd" "" { Text "C:/Documents and Settings/user/桌面/各个分模块/sysfenpin/sysfenpin.vhd" 29 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.872 ns" { tout2[5] Equal1~102 Equal1~103 tout2[10] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.872 ns" { tout2[5] Equal1~102 Equal1~103 tout2[10] } { 0.000ns 1.171ns 0.182ns 1.208ns } { 0.000ns 0.590ns 0.114ns 0.607ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.008 ns" { clk cplk~reg0 tout2[10] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "8.008 ns" { clk clk~out0 cplk~reg0 tout2[10] } { 0.000ns 0.000ns 0.550ns 4.343ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.008 ns" { clk cplk~reg0 tout2[5] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "8.008 ns" { clk clk~out0 cplk~reg0 tout2[5] } { 0.000ns 0.000ns 0.550ns 4.343ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk keyclk keyclk~reg0 11.734 ns register " "Info: tco from clock \"clk\" to destination pin \"keyclk\" through register \"keyclk~reg0\" is 11.734 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.008 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 8.008 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 12 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 12; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "sysfenpin.vhd" "" { Text "C:/Documents and Settings/user/桌面/各个分模块/sysfenpin/sysfenpin.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.935 ns) 2.954 ns cplk~reg0 2 REG LC_X5_Y2_N2 13 " "Info: 2: + IC(0.550 ns) + CELL(0.935 ns) = 2.954 ns; Loc. = LC_X5_Y2_N2; Fanout = 13; REG Node = 'cplk~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.485 ns" { clk cplk~reg0 } "NODE_NAME" } } { "sysfenpin.vhd" "" { Text "C:/Documents and Settings/user/桌面/各个分模块/sysfenpin/sysfenpin.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.343 ns) + CELL(0.711 ns) 8.008 ns keyclk~reg0 3 REG LC_X2_Y11_N4 1 " "Info: 3: + IC(4.343 ns) + CELL(0.711 ns) = 8.008 ns; Loc. = LC_X2_Y11_N4; Fanout = 1; REG Node = 'keyclk~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.054 ns" { cplk~reg0 keyclk~reg0 } "NODE_NAME" } } { "sysfenpin.vhd" "" { Text "C:/Documents and Settings/user/桌面/各个分模块/sysfenpin/sysfenpin.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 38.90 % ) " "Info: Total cell delay = 3.115 ns ( 38.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.893 ns ( 61.10 % ) " "Info: Total interconnect delay = 4.893 ns ( 61.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.008 ns" { clk cplk~reg0 keyclk~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "8.008 ns" { clk clk~out0 cplk~reg0 keyclk~reg0 } { 0.000ns 0.000ns 0.550ns 4.343ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "sysfenpin.vhd" "" { Text "C:/Documents and Settings/user/桌面/各个分模块/sysfenpin/sysfenpin.vhd" 29 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.502 ns + Longest register pin " "Info: + Longest register to pin delay is 3.502 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns keyclk~reg0 1 REG LC_X2_Y11_N4 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y11_N4; Fanout = 1; REG Node = 'keyclk~reg0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { keyclk~reg0 } "NODE_NAME" } } { "sysfenpin.vhd" "" { Text "C:/Documents and Settings/user/桌面/各个分模块/sysfenpin/sysfenpin.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.394 ns) + CELL(2.108 ns) 3.502 ns keyclk 2 PIN PIN_143 0 " "Info: 2: + IC(1.394 ns) + CELL(2.108 ns) = 3.502 ns; Loc. = PIN_143; Fanout = 0; PIN Node = 'keyclk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.502 ns" { keyclk~reg0 keyclk } "NODE_NAME" } } { "sysfenpin.vhd" "" { Text "C:/Documents and Settings/user/桌面/各个分模块/sysfenpin/sysfenpin.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns ( 60.19 % ) " "Info: Total cell delay = 2.108 ns ( 60.19 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.394 ns ( 39.81 % ) " "Info: Total interconnect delay = 1.394 ns ( 39.81 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.502 ns" { keyclk~reg0 keyclk } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.502 ns" { keyclk~reg0 keyclk } { 0.000ns 1.394ns } { 0.000ns 2.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.008 ns" { clk cplk~reg0 keyclk~reg0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "8.008 ns" { clk clk~out0 cplk~reg0 keyclk~reg0 } { 0.000ns 0.000ns 0.550ns 4.343ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.502 ns" { keyclk~reg0 keyclk } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.502 ns" { keyclk~reg0 keyclk } { 0.000ns 1.394ns } { 0.000ns 2.108ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Nov 30 12:16:33 2008 " "Info: Processing ended: Sun Nov 30 12:16:33 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}