corn.tan.qmsg

用VHDL语言编写的8*8点阵显示“北京08”的程序。可以用FPGA实现。可将程序当中的“北京08”改成别的汉字显示。

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version " "Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Dec 01 10:25:41 2008 " "Info: Processing started: Mon Dec 01 10:25:41 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off corn -c corn --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off corn -c corn --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "sel\[0\] q2\[7\] 13.823 ns Longest " "Info: Longest tpd from source pin \"sel\[0\]\" to destination pin \"q2\[7\]\" is 13.823 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns sel\[0\] 1 PIN PIN_7 13 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_7; Fanout = 13; PIN Node = 'sel\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sel[0] } "NODE_NAME" } } { "corn.vhd" "" { Text "F:/liudehua/corn/corn.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.157 ns) + CELL(0.590 ns) 7.216 ns Mux12~261 2 COMB LC_X2_Y10_N1 1 " "Info: 2: + IC(5.157 ns) + CELL(0.590 ns) = 7.216 ns; Loc. = LC_X2_Y10_N1; Fanout = 1; COMB Node = 'Mux12~261'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.747 ns" { sel[0] Mux12~261 } "NODE_NAME" } } { "corn.vhd" "" { Text "F:/liudehua/corn/corn.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.466 ns) + CELL(0.590 ns) 8.272 ns Mux12~262 3 COMB LC_X2_Y10_N2 1 " "Info: 3: + IC(0.466 ns) + CELL(0.590 ns) = 8.272 ns; Loc. = LC_X2_Y10_N2; Fanout = 1; COMB Node = 'Mux12~262'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.056 ns" { Mux12~261 Mux12~262 } "NODE_NAME" } } { "corn.vhd" "" { Text "F:/liudehua/corn/corn.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.427 ns) + CELL(2.124 ns) 13.823 ns q2\[7\] 4 PIN PIN_100 0 " "Info: 4: + IC(3.427 ns) + CELL(2.124 ns) = 13.823 ns; Loc. = PIN_100; Fanout = 0; PIN Node = 'q2\[7\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.551 ns" { Mux12~262 q2[7] } "NODE_NAME" } } { "corn.vhd" "" { Text "F:/liudehua/corn/corn.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.773 ns ( 34.53 % ) " "Info: Total cell delay = 4.773 ns ( 34.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.050 ns ( 65.47 % ) " "Info: Total interconnect delay = 9.050 ns ( 65.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "13.823 ns" { sel[0] Mux12~261 Mux12~262 q2[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "13.823 ns" { sel[0] sel[0]~out0 Mux12~261 Mux12~262 q2[7] } { 0.000ns 0.000ns 5.157ns 0.466ns 3.427ns } { 0.000ns 1.469ns 0.590ns 0.590ns 2.124ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Dec 01 10:25:41 2008 " "Info: Processing ended: Mon Dec 01 10:25:41 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}