edah.map.qmsg

用VHDL语言编写的8*8点阵显示“北京08”的程序。可以用FPGA实现。可将程序当中的“北京08”改成别的汉字显示。

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version " "Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Dec 01 10:29:49 2008 " "Info: Processing started: Mon Dec 01 10:29:49 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off EDAH -c EDAH " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off EDAH -c EDAH" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../sysfenpin/sysfenpin.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../sysfenpin/sysfenpin.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sysfenpin-rtl " "Info: Found design unit 1: sysfenpin-rtl" {  } { { "../sysfenpin/sysfenpin.vhd" "" { Text "F:/liudehua/sysfenpin/sysfenpin.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 sysfenpin " "Info: Found entity 1: sysfenpin" {  } { { "../sysfenpin/sysfenpin.vhd" "" { Text "F:/liudehua/sysfenpin/sysfenpin.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../saomiao/saomiao.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../saomiao/saomiao.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 saomiao-kkk " "Info: Found design unit 1: saomiao-kkk" {  } { { "../saomiao/saomiao.vhd" "" { Text "F:/liudehua/saomiao/saomiao.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 saomiao " "Info: Found entity 1: saomiao" {  } { { "../saomiao/saomiao.vhd" "" { Text "F:/liudehua/saomiao/saomiao.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../docor38a/docor38a.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../docor38a/docor38a.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 docor38a-aaa " "Info: Found design unit 1: docor38a-aaa" {  } { { "../docor38a/docor38a.vhd" "" { Text "F:/liudehua/docor38a/docor38a.vhd" 7 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 docor38a " "Info: Found entity 1: docor38a" {  } { { "../docor38a/docor38a.vhd" "" { Text "F:/liudehua/docor38a/docor38a.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../corn/corn.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../corn/corn.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 corn-corn_arc " "Info: Found design unit 1: corn-corn_arc" {  } { { "../corn/corn.vhd" "" { Text "F:/liudehua/corn/corn.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 corn " "Info: Found entity 1: corn" {  } { { "../corn/corn.vhd" "" { Text "F:/liudehua/corn/corn.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../chw/chw.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../chw/chw.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 chw-chw_arc " "Info: Found design unit 1: chw-chw_arc" {  } { { "../chw/chw.vhd" "" { Text "F:/liudehua/chw/chw.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 chw " "Info: Found entity 1: chw" {  } { { "../chw/chw.vhd" "" { Text "F:/liudehua/chw/chw.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "EDAH.vhd 2 1 " "Warning: Using design file EDAH.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 EDAH-one " "Info: Found design unit 1: EDAH-one" {  } { { "EDAH.vhd" "" { Text "F:/liudehua/EDAH/EDAH.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 EDAH " "Info: Found entity 1: EDAH" {  } { { "EDAH.vhd" "" { Text "F:/liudehua/EDAH/EDAH.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "EDAH " "Info: Elaborating entity \"EDAH\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sysfenpin sysfenpin:u0 " "Info: Elaborating entity \"sysfenpin\" for hierarchy \"sysfenpin:u0\"" {  } { { "EDAH.vhd" "u0" { Text "F:/liudehua/EDAH/EDAH.vhd" 35 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "chw chw:u1 " "Info: Elaborating entity \"chw\" for hierarchy \"chw:u1\"" {  } { { "EDAH.vhd" "u1" { Text "F:/liudehua/EDAH/EDAH.vhd" 36 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "saomiao saomiao:u2 " "Info: Elaborating entity \"saomiao\" for hierarchy \"saomiao:u2\"" {  } { { "EDAH.vhd" "u2" { Text "F:/liudehua/EDAH/EDAH.vhd" 37 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "corn corn:u3 " "Info: Elaborating entity \"corn\" for hierarchy \"corn:u3\"" {  } { { "EDAH.vhd" "u3" { Text "F:/liudehua/EDAH/EDAH.vhd" 38 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "docor38a docor38a:u4 " "Info: Elaborating entity \"docor38a\" for hierarchy \"docor38a:u4\"" {  } { { "EDAH.vhd" "u4" { Text "F:/liudehua/EDAH/EDAH.vhd" 39 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "sysfenpin:u0\|tout2\[0\] saomiao:u2\|tmp\[0\] " "Info: Duplicate register \"sysfenpin:u0\|tout2\[0\]\" merged to single register \"saomiao:u2\|tmp\[0\]\"" {  } { { "../sysfenpin/sysfenpin.vhd" "" { Text "F:/liudehua/sysfenpin/sysfenpin.vhd" 29 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "sysfenpin:u0\|tout2\[1\] saomiao:u2\|tmp\[1\] " "Info: Duplicate register \"sysfenpin:u0\|tout2\[1\]\" merged to single register \"saomiao:u2\|tmp\[1\]\"" {  } { { "../sysfenpin/sysfenpin.vhd" "" { Text "F:/liudehua/sysfenpin/sysfenpin.vhd" 29 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "sysfenpin:u0\|tout2\[2\] saomiao:u2\|tmp\[2\] " "Info: Duplicate register \"sysfenpin:u0\|tout2\[2\]\" merged to single register \"saomiao:u2\|tmp\[2\]\"" {  } { { "../sysfenpin/sysfenpin.vhd" "" { Text "F:/liudehua/sysfenpin/sysfenpin.vhd" 29 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "105 " "Info: Implemented 105 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "16 " "Info: Implemented 16 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "88 " "Info: Implemented 88 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Dec 01 10:29:52 2008 " "Info: Processing ended: Mon Dec 01 10:29:52 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}