divclk_5k.vhd

many application on kit SP-3: VGA, digital clock, counter, interface PS2....

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity divclk_5k is
    Port ( clk0 : in  STD_LOGIC;
           clk1 : out STD_LOGIC);
end divclk_5k;

architecture Behavioral of divclk_5k is
	CONSTANT max: INTEGER := 10000;
	CONSTANT half: INTEGER := max/2;
	SIGNAL count: INTEGER RANGE 0 TO max;
	SIGNAL toggle: STD_LOGIC;
	
begin
	c1:PROCESS
	BEGIN
		WAIT UNTIL clk0'EVENT and clk0='1';
		IF count < max THEN
			count <= count + 1;
		ELSE
			count <= 1;
		END IF;
		
		IF count <= half THEN
			toggle <= '0';
		ELSE
			toggle <= '1';
		END IF;
		clk1 <= toggle;
	END PROCESS;	
end Behavioral;