comtx.vhd

many application on kit SP-3: VGA, digital clock, counter, interface PS2....

library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;

entity ComTx is  
  port(clk : in  std_logic;
    enaTx : in std_logic;
    DataIn : in std_logic_vector(7 downto 0);   
    bitout : out std_logic);
end ComTx;

architecture a of ComTx is
    type state_type is (idle, txBit);
    signal state : state_type;
	 signal clk5 :  std_logic;
	 
	 component divclk_5k 
		Port ( clk0 : in  STD_LOGIC;
				clk1 : out STD_LOGIC);
	 end  component;				
begin  
	A1: divclk_5k port map (clk,clk5);
	
process (clk5)
   -- variables change value imediately
   variable index : integer range 0 to 10 ;
   variable temp : std_logic;
   variable data : std_logic_vector (10 downto 1);
begin  -- process    
    if (clk5'event and clk5 ='1')then
      case state is
        when idle =>
	        if(enaTx = '1')then
					state <= txBit;
					data := '1' & DataIn & '0';  -- add start bit=0 and stop bit=1
	        else 
		        	state <= idle; 
		         index := 0;
		         temp :='1';
	        end if;             
        when txBit =>
          	index := index + 1;
          	if (index < 10) then
		          	state <= txBit;		          	
		          	temp := '0';
          	elsif(index = 10) then
		            state <= idle; 
		            index := 0;
		            temp := '1';  
				end if;
        when others => state <= idle; 
      end case;
		if(temp = '1')then
			bitout <= '1';
		else
			bitout <= data(index);
		end if;
	 end if;   
end process;
end a;