divclk_3.vhd

many application on kit SP-3: VGA, digital clock, counter, interface PS2....

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity divclk_3 is
    Port ( clk0 : in  STD_LOGIC;
           clk2,clk3 : out STD_LOGIC);
end divclk_3;

architecture Behavioral of divclk_3 is
--	CONSTANT max: INTEGER := 50000000;
--	CONSTANT half: INTEGER := max/2;
--	SIGNAL count: INTEGER RANGE 0 TO max;
--	SIGNAL toggle: STD_LOGIC;
	CONSTANT max1: INTEGER := 100000000;
	CONSTANT half1: INTEGER := max1/2;
	SIGNAL count1: INTEGER RANGE 0 TO max1;
	SIGNAL toggle1: STD_LOGIC;
	CONSTANT max2: INTEGER := 250000;
	CONSTANT half2: INTEGER := max2/2;
	SIGNAL count2: INTEGER RANGE 0 TO max2;
	SIGNAL toggle2: STD_LOGIC;
begin
--	c1:PROCESS
--	BEGIN
--		WAIT UNTIL clk0'EVENT and clk0='1';
--		IF count < max THEN
--			count <= count + 1;
--		ELSE
--			count <= 1;
--		END IF;
--		
--		IF count <= half THEN
--			toggle <= '0';
--		ELSE
--			toggle <= '1';
--		END IF;
--		clk1 <= toggle;
--	END PROCESS;
	
	c2:PROCESS
	BEGIN
		WAIT UNTIL clk0'EVENT and clk0='1';
		IF count1 < max1 THEN
			count1 <= count1 + 1;
		ELSE
			count1 <= 1;
		END IF;
		
		IF count1 <= half1 THEN
			toggle1 <= '0';
		ELSE
			toggle1 <= '1';
		END IF;
		clk2 <= toggle1;
	END PROCESS;
	
	c3:PROCESS
	BEGIN
		WAIT UNTIL clk0'EVENT and clk0='1';
		IF count2 < max2 THEN
			count2 <= count2 + 1;
		ELSE
			count2 <= 1;
		END IF;
		
		IF count2 <= half2 THEN
			toggle2 <= '0';
		ELSE
			toggle2 <= '1';
		END IF;
		clk3 <= toggle2;
	END PROCESS;
end Behavioral;