topkbvgachar.vhd

many application on kit SP-3: VGA, digital clock, counter, interface PS2....

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity TopKBVGAchar is
    Port ( clk,ps2_data,ps2_clk : in  STD_LOGIC;
				hs,vs : out  STD_LOGIC;
           RGB : out  STD_LOGIC_VECTOR (2 downto 0));
end TopKBVGAchar;

architecture Behavioral of TopKBVGAchar is
	component KeyVga  --100_000
		generic(FREQ : natural := 50000 );   
		port(clk  : in  std_logic;    
			rdy  : buffer  std_logic;  
			ps2_clk  : in  std_logic;           
			ps2_data : in  std_logic;           
			cnt       : out std_logic_vector(4 downto 0);  
			sccode   : out std_logic_vector(7 downto 0));
	end component;
	
	component VGA_Module 
    Port ( clk50_in : in std_logic;
				sc : in std_logic_vector(7 downto 0);
				cntchar :in std_logic_vector(4 downto 0);  
           Red_out : out std_logic;
           Green_out : out std_logic;
           Blue_out : out std_logic;
           hs_out : out std_logic;
           vs_out : out std_logic);
	end component;
	signal scode:std_logic_vector(7 downto 0);
	signal rdy :std_logic;
	signal cnt1 : std_logic_vector(4 downto 0);  
begin
	Q1: keyVga port map (clk,rdy,ps2_clk,ps2_data,cnt1,scode);
	Q2: VGA_Module port map (clk,scode,cnt1,RGB(2),RGB(1),RGB(0),hs,vs);
end Behavioral;