countsp.vhd

many application on kit SP-3: VGA, digital clock, counter, interface PS2....

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Countsp is
    Port ( clk,SW1,SW0,SW2 : in  std_logic;
    		  BCD0,BCD1,BCD2,BCD3:out std_logic_VECTOR (3 downto 0));
end Countsp;

architecture Behavior of Countsp is
	signal cnt0,cnt1,cnt2,cnt3 : std_logic_vector (3 downto 0);
begin
	process(clk,SW1,SW0,SW2)
	begin
		if clk'event and clk='1' then 
			if SW0='1' and SW1='1' and SW2='1' then
				cnt0<="0000";
				cnt1<="0000";
				cnt2<="0000";
				cnt3<="0000";		
			else
				if cnt0="1001" then	--dem 9	(hang don vi)
					 cnt0<="0000";
					 if cnt1="1001" then		--dem 9(hang chuc)
							cnt1<="0000";
							if cnt2="1001" then	--dem 9(hang tram)
									cnt2<="0000";
									if cnt3="1001" then
										cnt3<="0000";		
									else	
										cnt3<=cnt3 + '1';
									end if;		--cnt3							
							else
									cnt2<=cnt2 + '1';	
							end if;	--cnt2
					 else
							cnt1<=cnt1 + '1';
					 end if;	--cnt1
				else
					 cnt0 <= cnt0 + '1';
				end if;		--cnt0
			end if;			--reset ena
		end if;				--clk
		--dieu kien reset lai bo dem la dem toi 1000
		if (cnt3="0001" and cnt2="0000" 
				and cnt1="0000" and cnt0="0001") then
			cnt0<="0000";
			cnt1<="0000";
			cnt2<="0000";
			cnt3<="0000";
		end if;						
	end process;
	bcd0<=cnt0;
	bcd1<=cnt1;
	bcd2<=cnt2;
	bcd3<=cnt3;
end Behavior;