divclk_1hz.vhd

来自「many application on kit SP-3: VGA, digit」· VHDL 代码 · 共 36 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity divclk_1hz is
    Port ( clk1 : in  STD_LOGIC;
           clk2 : out STD_LOGIC);
end divclk_1hz;

architecture Behavioral of divclk_1hz is
	CONSTANT max: INTEGER := 50000000;
	CONSTANT half: INTEGER := max/2;
	SIGNAL count: INTEGER RANGE 1 TO max;
	SIGNAL toggle: STD_LOGIC;
begin
	PROCESS
	BEGIN
		WAIT UNTIL clk1'EVENT and clk1='1';
		IF count < max THEN
			count <= count + 1;
		ELSE
			count <= 1;
		END IF;
		
		IF count <= half THEN
			toggle <= '0';
		ELSE
			toggle <= '1';
		END IF;
		clk2 <= toggle;
	END PROCESS;

end Behavioral;