adc0820.fit.qmsg

AD0820小程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon May 19 18:11:44 2008 " "Info: Processing started: Mon May 19 18:11:44 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off adc0820 -c adc0820 " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off adc0820 -c adc0820" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "adc0820 EP1C12Q240C8 " "Info: Selected device EP1C12Q240C8 for design \"adc0820\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C6Q240C8 " "Info: Device EP1C6Q240C8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "9 10 " "Info: No exact pin location assignment(s) for 9 pins of 10 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "rd " "Info: Pin rd not assigned to an exact location on the device" {  } { { "top.bdf" "" { Schematic "E:/vhdl code/ad0820new/top.bdf" { { 80 576 752 96 "rd" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "rd" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc0820" "UNKNOWN" "V1" "E:/vhdl code/ad0820new/db/adc0820.quartus_db" { Floorplan "E:/vhdl code/ad0820new/" "" "" { rd } "NODE_NAME" } "" } } { "E:/vhdl code/ad0820new/adc0820.fld" "" { Floorplan "E:/vhdl code/ad0820new/adc0820.fld" "" "" { rd } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "d\[7\] " "Info: Pin d\[7\] not assigned to an exact location on the device" {  } { { "top.bdf" "" { Schematic "E:/vhdl code/ad0820new/top.bdf" { { 224 136 304 240 "d\[7..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "d\[7\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc0820" "UNKNOWN" "V1" "E:/vhdl code/ad0820new/db/adc0820.quartus_db" { Floorplan "E:/vhdl code/ad0820new/" "" "" { d[7] } "NODE_NAME" } "" } } { "E:/vhdl code/ad0820new/adc0820.fld" "" { Floorplan "E:/vhdl code/ad0820new/adc0820.fld" "" "" { d[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "d\[6\] " "Info: Pin d\[6\] not assigned to an exact location on the device" {  } { { "top.bdf" "" { Schematic "E:/vhdl code/ad0820new/top.bdf" { { 224 136 304 240 "d\[7..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "d\[6\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc0820" "UNKNOWN" "V1" "E:/vhdl code/ad0820new/db/adc0820.quartus_db" { Floorplan "E:/vhdl code/ad0820new/" "" "" { d[6] } "NODE_NAME" } "" } } { "E:/vhdl code/ad0820new/adc0820.fld" "" { Floorplan "E:/vhdl code/ad0820new/adc0820.fld" "" "" { d[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "d\[5\] " "Info: Pin d\[5\] not assigned to an exact location on the device" {  } { { "top.bdf" "" { Schematic "E:/vhdl code/ad0820new/top.bdf" { { 224 136 304 240 "d\[7..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "d\[5\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc0820" "UNKNOWN" "V1" "E:/vhdl code/ad0820new/db/adc0820.quartus_db" { Floorplan "E:/vhdl code/ad0820new/" "" "" { d[5] } "NODE_NAME" } "" } } { "E:/vhdl code/ad0820new/adc0820.fld" "" { Floorplan "E:/vhdl code/ad0820new/adc0820.fld" "" "" { d[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "d\[4\] " "Info: Pin d\[4\] not assigned to an exact location on the device" {  } { { "top.bdf" "" { Schematic "E:/vhdl code/ad0820new/top.bdf" { { 224 136 304 240 "d\[7..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "d\[4\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc0820" "UNKNOWN" "V1" "E:/vhdl code/ad0820new/db/adc0820.quartus_db" { Floorplan "E:/vhdl code/ad0820new/" "" "" { d[4] } "NODE_NAME" } "" } } { "E:/vhdl code/ad0820new/adc0820.fld" "" { Floorplan "E:/vhdl code/ad0820new/adc0820.fld" "" "" { d[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "d\[3\] " "Info: Pin d\[3\] not assigned to an exact location on the device" {  } { { "top.bdf" "" { Schematic "E:/vhdl code/ad0820new/top.bdf" { { 224 136 304 240 "d\[7..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "d\[3\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc0820" "UNKNOWN" "V1" "E:/vhdl code/ad0820new/db/adc0820.quartus_db" { Floorplan "E:/vhdl code/ad0820new/" "" "" { d[3] } "NODE_NAME" } "" } } { "E:/vhdl code/ad0820new/adc0820.fld" "" { Floorplan "E:/vhdl code/ad0820new/adc0820.fld" "" "" { d[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "d\[2\] " "Info: Pin d\[2\] not assigned to an exact location on the device" {  } { { "top.bdf" "" { Schematic "E:/vhdl code/ad0820new/top.bdf" { { 224 136 304 240 "d\[7..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "d\[2\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc0820" "UNKNOWN" "V1" "E:/vhdl code/ad0820new/db/adc0820.quartus_db" { Floorplan "E:/vhdl code/ad0820new/" "" "" { d[2] } "NODE_NAME" } "" } } { "E:/vhdl code/ad0820new/adc0820.fld" "" { Floorplan "E:/vhdl code/ad0820new/adc0820.fld" "" "" { d[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "d\[1\] " "Info: Pin d\[1\] not assigned to an exact location on the device" {  } { { "top.bdf" "" { Schematic "E:/vhdl code/ad0820new/top.bdf" { { 224 136 304 240 "d\[7..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "d\[1\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc0820" "UNKNOWN" "V1" "E:/vhdl code/ad0820new/db/adc0820.quartus_db" { Floorplan "E:/vhdl code/ad0820new/" "" "" { d[1] } "NODE_NAME" } "" } } { "E:/vhdl code/ad0820new/adc0820.fld" "" { Floorplan "E:/vhdl code/ad0820new/adc0820.fld" "" "" { d[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "d\[0\] " "Info: Pin d\[0\] not assigned to an exact location on the device" {  } { { "top.bdf" "" { Schematic "E:/vhdl code/ad0820new/top.bdf" { { 224 136 304 240 "d\[7..0\]" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "d\[0\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc0820" "UNKNOWN" "V1" "E:/vhdl code/ad0820new/db/adc0820.quartus_db" { Floorplan "E:/vhdl code/ad0820new/" "" "" { d[0] } "NODE_NAME" } "" } } { "E:/vhdl code/ad0820new/adc0820.fld" "" { Floorplan "E:/vhdl code/ad0820new/adc0820.fld" "" "" { d[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0}  } {  } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0}  } {  } 0 0 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0 0 "Performing register packing on registers with non-logic cell location assignments" 0 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0 0 "Completed register packing on registers with non-logic cell location assignments" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources" {  } {  } 0 0 "DQS I/O pins require %1!d! global routing resources" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk Global clock in PIN 153 " "Info: Automatically promoted signal \"clk\" to use Global clock in PIN 153" {  } { { "top.bdf" "" { Schematic "E:/vhdl code/ad0820new/top.bdf" { { 136 -48 120 152 "clk" "" } } } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "div:inst\|clk_tmp Global clock " "Info: Automatically promoted some destinations of signal \"div:inst\|clk_tmp\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "div:inst\|clk_tmp " "Info: Destination \"div:inst\|clk_tmp\" may be non-global or may not use global clock" {  } { { "div.vhd" "" { Text "E:/vhdl code/ad0820new/div.vhd" 23 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "div.vhd" "" { Text "E:/vhdl code/ad0820new/div.vhd" 23 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "adc0820:inst1\|clko Global clock " "Info: Automatically promoted signal \"adc0820:inst1\|clko\" to use Global clock" {  } { { "adc0820.vhd" "" { Text "E:/vhdl code/ad0820new/adc0820.vhd" 20 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0 0 "Started Fast Input/Output/OE register processing" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0 0 "Finished Fast Input/Output/OE register processing" 0 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0}