display1.vhd

来自「AD0820小程序」· VHDL 代码 · 共 49 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.mypack.all;      
use ieee.std_logic_unsigned.all;

entity display1 is
	port(
		clk: in std_logic;
		D: in std_logic_vector(7 downto 0);
		RD: out std_logic;

		en:in bit;
		segout:out std_logic_vector(31 downto 0)
		);
		
end;


architecture one of display1 is

signal seg :std_logic_vector(31 downto 0);
signal maxmindata:std_logic_vector(7 downto 0);
signal LOCK:std_logic;
		
component ADC0820
	port(
		clk: in std_logic;
		D: in std_logic_vector(7 downto 0);
		RD: out std_logic;
		LOCK: out std_logic;
		Q: out std_logic_vector(7 downto 0)
	);
end component;

begin

u1: ADC0820 port map(clk=>clk,D=>D,RD=>RD,LOCK=>LOCK,Q=>maxmindata);

	process(maxmindata,seg,en)
	begin
	if  en='0' then
		seg<="10111011101110111011101110111011";
		else
			seg<="101110111011101110111011"& change(maxmindata);
	end if;
	end process;
	segout<=seg;
end;