adc0820.map.qmsg

AD0820小程序

{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "U7279:inst2\|FPGA_7279:inst3\|data_start High " "Info: Power-up level of register \"U7279:inst2\|FPGA_7279:inst3\|data_start\" is not specified -- using power-up level of High to minimize register" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/ad0820new/FPGA_7279.vhd" 63 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "U7279:inst2\|FPGA_7279:inst3\|data_start data_in VCC " "Warning: Reduced register \"U7279:inst2\|FPGA_7279:inst3\|data_start\" with stuck data_in port to stuck value VCC" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/ad0820new/FPGA_7279.vhd" 63 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "U7279:inst2\|FPGA_7279:inst3\|cmd_tmp1\[7\] High " "Info: Power-up level of register \"U7279:inst2\|FPGA_7279:inst3\|cmd_tmp1\[7\]\" is not specified -- using power-up level of High to minimize register" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/ad0820new/FPGA_7279.vhd" 196 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "U7279:inst2\|FPGA_7279:inst3\|cmd_tmp1\[7\] data_in VCC " "Warning: Reduced register \"U7279:inst2\|FPGA_7279:inst3\|cmd_tmp1\[7\]\" with stuck data_in port to stuck value VCC" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/ad0820new/FPGA_7279.vhd" 196 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "U7279:inst2\|FPGA_7279:inst3\|cmd_tmp1\[6\] data_in GND " "Warning: Reduced register \"U7279:inst2\|FPGA_7279:inst3\|cmd_tmp1\[6\]\" with stuck data_in port to stuck value GND" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/ad0820new/FPGA_7279.vhd" 196 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "U7279:inst2\|FPGA_7279:inst3\|cmd_tmp1\[5\] data_in GND " "Warning: Reduced register \"U7279:inst2\|FPGA_7279:inst3\|cmd_tmp1\[5\]\" with stuck data_in port to stuck value GND" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/ad0820new/FPGA_7279.vhd" 196 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "U7279:inst2\|FPGA_7279:inst3\|cmd_tmp1\[4\] High " "Info: Power-up level of register \"U7279:inst2\|FPGA_7279:inst3\|cmd_tmp1\[4\]\" is not specified -- using power-up level of High to minimize register" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/ad0820new/FPGA_7279.vhd" 196 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "U7279:inst2\|FPGA_7279:inst3\|cmd_tmp1\[4\] data_in VCC " "Warning: Reduced register \"U7279:inst2\|FPGA_7279:inst3\|cmd_tmp1\[4\]\" with stuck data_in port to stuck value VCC" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/ad0820new/FPGA_7279.vhd" 196 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "U7279:inst2\|FPGA_7279:inst3\|cmd_tmp1\[3\] data_in GND " "Warning: Reduced register \"U7279:inst2\|FPGA_7279:inst3\|cmd_tmp1\[3\]\" with stuck data_in port to stuck value GND" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/ad0820new/FPGA_7279.vhd" 196 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "U7279:inst2\|FPGA_7279:inst3\|data_start_tmp High " "Info: Power-up level of register \"U7279:inst2\|FPGA_7279:inst3\|data_start_tmp\" is not specified -- using power-up level of High to minimize register" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/ad0820new/FPGA_7279.vhd" 65 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "U7279:inst2\|FPGA_7279:inst3\|data_start_tmp data_in VCC " "Warning: Reduced register \"U7279:inst2\|FPGA_7279:inst3\|data_start_tmp\" with stuck data_in port to stuck value VCC" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/ad0820new/FPGA_7279.vhd" 65 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|top\|display1:inst3\|adc0820:u1\|fsm3 6 " "Info: State machine \"\|top\|display1:inst3\|adc0820:u1\|fsm3\" contains 6 states" {  } { { "adc0820.vhd" "" { Text "E:/vhdl code/ad0820new/adc0820.vhd" 18 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|top\|display1:inst3\|adc0820:u1\|current_state 6 " "Info: State machine \"\|top\|display1:inst3\|adc0820:u1\|current_state\" contains 6 states" {  } { { "adc0820.vhd" "" { Text "E:/vhdl code/ad0820new/adc0820.vhd" 18 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|top\|U7279:inst2\|Display8:inst5\|state 7 " "Info: State machine \"\|top\|U7279:inst2\|Display8:inst5\|state\" contains 7 states" {  } { { "Display8.vhd" "" { Text "E:/vhdl code/ad0820new/Display8.vhd" 21 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|top\|U7279:inst2\|FPGA_7279:inst3\|state 12 " "Info: State machine \"\|top\|U7279:inst2\|FPGA_7279:inst3\|state\" contains 12 states" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/ad0820new/FPGA_7279.vhd" 74 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|top\|U7279:inst2\|FPGA_7279:inst3\|state1 3 " "Info: State machine \"\|top\|U7279:inst2\|FPGA_7279:inst3\|state1\" contains 3 states" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/ad0820new/FPGA_7279.vhd" 76 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|top\|adc0820:inst1\|fsm3 6 " "Info: State machine \"\|top\|adc0820:inst1\|fsm3\" contains 6 states" {  } { { "adc0820.vhd" "" { Text "E:/vhdl code/ad0820new/adc0820.vhd" 18 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}