adc0820.map.qmsg

AD0820小程序

{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Din Display8.vhd(30) " "Warning (10492): VHDL Process Statement warning at Display8.vhd(30): signal \"Din\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "Display8.vhd" "" { Text "E:/vhdl code/ad0820new/Display8.vhd" 30 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Din Display8.vhd(31) " "Warning (10492): VHDL Process Statement warning at Display8.vhd(31): signal \"Din\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "Display8.vhd" "" { Text "E:/vhdl code/ad0820new/Display8.vhd" 31 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Din Display8.vhd(32) " "Warning (10492): VHDL Process Statement warning at Display8.vhd(32): signal \"Din\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "Display8.vhd" "" { Text "E:/vhdl code/ad0820new/Display8.vhd" 32 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Din Display8.vhd(33) " "Warning (10492): VHDL Process Statement warning at Display8.vhd(33): signal \"Din\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "Display8.vhd" "" { Text "E:/vhdl code/ad0820new/Display8.vhd" 33 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Din Display8.vhd(34) " "Warning (10492): VHDL Process Statement warning at Display8.vhd(34): signal \"Din\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "Display8.vhd" "" { Text "E:/vhdl code/ad0820new/Display8.vhd" 34 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "Display8.vhd(35) " "Info (10425): VHDL Case Statement information at Display8.vhd(35): OTHERS choice is never selected" {  } { { "Display8.vhd" "" { Text "E:/vhdl code/ad0820new/Display8.vhd" 35 0 0 } }  } 0 10425 "VHDL Case Statement information at %1!s!: OTHERS choice is never selected" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "div U7279:inst2\|div:inst " "Info: Elaborating entity \"div\" for hierarchy \"U7279:inst2\|div:inst\"" {  } { { "U7279.bdf" "inst" { Schematic "E:/vhdl code/ad0820new/U7279.bdf" { { 256 288 384 336 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "div U7279:inst2\|div:inst1 " "Info: Elaborating entity \"div\" for hierarchy \"U7279:inst2\|div:inst1\"" {  } { { "U7279.bdf" "inst1" { Schematic "E:/vhdl code/ad0820new/U7279.bdf" { { 152 528 624 232 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "display1 display1:inst3 " "Info: Elaborating entity \"display1\" for hierarchy \"display1:inst3\"" {  } { { "top.bdf" "inst3" { Schematic "E:/vhdl code/ad0820new/top.bdf" { { 368 104 256 464 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "LOCK display1.vhd(24) " "Warning (10036): Verilog HDL or VHDL warning at display1.vhd(24): object \"LOCK\" assigned a value but never read" {  } { { "display1.vhd" "" { Text "E:/vhdl code/ad0820new/display1.vhd" 24 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "U7279:inst2\|FPGA_7279:inst3\|cmd_tmp\[7\] High " "Info: Power-up level of register \"U7279:inst2\|FPGA_7279:inst3\|cmd_tmp\[7\]\" is not specified -- using power-up level of High to minimize register" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/ad0820new/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "U7279:inst2\|FPGA_7279:inst3\|cmd_tmp\[7\] data_in VCC " "Warning: Reduced register \"U7279:inst2\|FPGA_7279:inst3\|cmd_tmp\[7\]\" with stuck data_in port to stuck value VCC" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/ad0820new/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "U7279:inst2\|FPGA_7279:inst3\|cmd_tmp\[6\] data_in GND " "Warning: Reduced register \"U7279:inst2\|FPGA_7279:inst3\|cmd_tmp\[6\]\" with stuck data_in port to stuck value GND" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/ad0820new/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "U7279:inst2\|FPGA_7279:inst3\|cmd_tmp\[5\] data_in GND " "Warning: Reduced register \"U7279:inst2\|FPGA_7279:inst3\|cmd_tmp\[5\]\" with stuck data_in port to stuck value GND" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/ad0820new/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "U7279:inst2\|FPGA_7279:inst3\|cmd_tmp\[4\] High " "Info: Power-up level of register \"U7279:inst2\|FPGA_7279:inst3\|cmd_tmp\[4\]\" is not specified -- using power-up level of High to minimize register" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/ad0820new/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "U7279:inst2\|FPGA_7279:inst3\|cmd_tmp\[4\] data_in VCC " "Warning: Reduced register \"U7279:inst2\|FPGA_7279:inst3\|cmd_tmp\[4\]\" with stuck data_in port to stuck value VCC" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/ad0820new/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "U7279:inst2\|FPGA_7279:inst3\|cmd_tmp\[3\] data_in GND " "Warning: Reduced register \"U7279:inst2\|FPGA_7279:inst3\|cmd_tmp\[3\]\" with stuck data_in port to stuck value GND" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/ad0820new/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}