adc0820.map.qmsg

AD0820小程序

{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "Q adc0820.vhd(22) " "Warning (10631): VHDL Process Statement warning at adc0820.vhd(22): signal or variable \"Q\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"Q\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "adc0820.vhd" "" { Text "E:/vhdl code/ad0820new/adc0820.vhd" 22 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: signal or variable \"%1!s!\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"%1!s!\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "div div:inst " "Info: Elaborating entity \"div\" for hierarchy \"div:inst\"" {  } { { "top.bdf" "inst" { Schematic "E:/vhdl code/ad0820new/top.bdf" { { 80 208 304 176 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "U7279 U7279:inst2 " "Info: Elaborating entity \"U7279\" for hierarchy \"U7279:inst2\"" {  } { { "top.bdf" "inst2" { Schematic "E:/vhdl code/ad0820new/top.bdf" { { 304 520 728 432 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "FPGA_7279.vhd 2 1 " "Warning: Using design file FPGA_7279.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 FPGA_7279-behav " "Info: Found design unit 1: FPGA_7279-behav" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/ad0820new/FPGA_7279.vhd" 30 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 FPGA_7279 " "Info: Found entity 1: FPGA_7279" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/ad0820new/FPGA_7279.vhd" 8 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "FPGA_7279 U7279:inst2\|FPGA_7279:inst3 " "Info: Elaborating entity \"FPGA_7279\" for hierarchy \"U7279:inst2\|FPGA_7279:inst3\"" {  } { { "U7279.bdf" "inst3" { Schematic "E:/vhdl code/ad0820new/U7279.bdf" { { 304 520 704 480 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "cmd_7279 FPGA_7279.vhd(47) " "Info (10035): Verilog HDL or VHDL information at FPGA_7279.vhd(47): object \"cmd_7279\" declared but not used" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/ad0820new/FPGA_7279.vhd" 47 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "f_edge_cnt FPGA_7279.vhd(59) " "Info (10035): Verilog HDL or VHDL information at FPGA_7279.vhd(59): object \"f_edge_cnt\" declared but not used" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/ad0820new/FPGA_7279.vhd" 59 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "cmd_start_tmp FPGA_7279.vhd(64) " "Warning (10036): Verilog HDL or VHDL warning at FPGA_7279.vhd(64): object \"cmd_start_tmp\" assigned a value but never read" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/ad0820new/FPGA_7279.vhd" 64 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "seg_r FPGA_7279.vhd(68) " "Info (10035): Verilog HDL or VHDL information at FPGA_7279.vhd(68): object \"seg_r\" declared but not used" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/ad0820new/FPGA_7279.vhd" 68 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "FPGA_7279.vhd(188) " "Info (10425): VHDL Case Statement information at FPGA_7279.vhd(188): OTHERS choice is never selected" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/ad0820new/FPGA_7279.vhd" 188 0 0 } }  } 0 10425 "VHDL Case Statement information at %1!s!: OTHERS choice is never selected" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "RD_N FPGA_7279.vhd(226) " "Warning (10492): VHDL Process Statement warning at FPGA_7279.vhd(226): signal \"RD_N\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/ad0820new/FPGA_7279.vhd" 226 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "FPGA_7279.vhd(276) " "Info (10425): VHDL Case Statement information at FPGA_7279.vhd(276): OTHERS choice is never selected" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/ad0820new/FPGA_7279.vhd" 276 0 0 } }  } 0 10425 "VHDL Case Statement information at %1!s!: OTHERS choice is never selected" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "Display8.vhd 2 1 " "Warning: Using design file Display8.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Display8-one " "Info: Found design unit 1: Display8-one" {  } { { "Display8.vhd" "" { Text "E:/vhdl code/ad0820new/Display8.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 Display8 " "Info: Found entity 1: Display8" {  } { { "Display8.vhd" "" { Text "E:/vhdl code/ad0820new/Display8.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Display8 U7279:inst2\|Display8:inst5 " "Info: Elaborating entity \"Display8\" for hierarchy \"U7279:inst2\|Display8:inst5\"" {  } { { "U7279.bdf" "inst5" { Schematic "E:/vhdl code/ad0820new/U7279.bdf" { { 368 256 424 464 "inst5" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Din Display8.vhd(27) " "Warning (10492): VHDL Process Statement warning at Display8.vhd(27): signal \"Din\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "Display8.vhd" "" { Text "E:/vhdl code/ad0820new/Display8.vhd" 27 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Din Display8.vhd(28) " "Warning (10492): VHDL Process Statement warning at Display8.vhd(28): signal \"Din\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "Display8.vhd" "" { Text "E:/vhdl code/ad0820new/Display8.vhd" 28 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Din Display8.vhd(29) " "Warning (10492): VHDL Process Statement warning at Display8.vhd(29): signal \"Din\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "Display8.vhd" "" { Text "E:/vhdl code/ad0820new/Display8.vhd" 29 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}