adc0820.map.qmsg

AD0820小程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon May 19 18:11:39 2008 " "Info: Processing started: Mon May 19 18:11:39 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off adc0820 -c adc0820 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off adc0820 -c adc0820" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "U7279.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file U7279.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 U7279 " "Info: Found entity 1: U7279" {  } { { "U7279.bdf" "" { Schematic "E:/vhdl code/ad0820new/U7279.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ADC0820.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ADC0820.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ADC0820-one " "Info: Found design unit 1: ADC0820-one" {  } { { "ADC0820.vhd" "" { Text "E:/vhdl code/ad0820new/ADC0820.vhd" 16 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 adc0820 " "Info: Found entity 1: adc0820" {  } { { "ADC0820.vhd" "" { Text "E:/vhdl code/ad0820new/ADC0820.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "div.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file div.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 div-behav " "Info: Found design unit 1: div-behav" {  } { { "div.vhd" "" { Text "E:/vhdl code/ad0820new/div.vhd" 16 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 div " "Info: Found entity 1: div" {  } { { "div.vhd" "" { Text "E:/vhdl code/ad0820new/div.vhd" 10 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "top.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file top.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 top " "Info: Found entity 1: top" {  } { { "top.bdf" "" { Schematic "E:/vhdl code/ad0820new/top.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "chang.vhd 2 0 " "Info: Found 2 design units, including 0 entities, in source file chang.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 mypack " "Info: Found design unit 1: mypack" {  } { { "chang.vhd" "" { Text "E:/vhdl code/ad0820new/chang.vhd" 6 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 mypack-body " "Info: Found design unit 2: mypack-body" {  } { { "chang.vhd" "" { Text "E:/vhdl code/ad0820new/chang.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "display1.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file display1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 display1-one " "Info: Found design unit 1: display1-one" {  } { { "display1.vhd" "" { Text "E:/vhdl code/ad0820new/display1.vhd" 20 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 display1 " "Info: Found entity 1: display1" {  } { { "display1.vhd" "" { Text "E:/vhdl code/ad0820new/display1.vhd" 7 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Block2.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file Block2.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 Block2 " "Info: Found entity 1: Block2" {  } { { "Block2.bdf" "" { Schematic "E:/vhdl code/ad0820new/Block2.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "top " "Info: Elaborating entity \"top\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "KEY7279 U7279 inst2 " "Warning: Port \"KEY7279\" of type U7279 and instance \"inst2\" is missing source signal" {  } { { "top.bdf" "" { Schematic "E:/vhdl code/ad0820new/top.bdf" { { 304 520 728 432 "inst2" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "DAT7279 U7279 inst2 " "Warning: Port \"DAT7279\" of type U7279 and instance \"inst2\" is missing source signal" {  } { { "top.bdf" "" { Schematic "E:/vhdl code/ad0820new/top.bdf" { { 304 520 728 432 "inst2" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "adc0820 adc0820:inst1 " "Info: Elaborating entity \"adc0820\" for hierarchy \"adc0820:inst1\"" {  } { { "top.bdf" "inst1" { Schematic "E:/vhdl code/ad0820new/top.bdf" { { 80 408 528 176 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "D adc0820.vhd(42) " "Warning (10492): VHDL Process Statement warning at adc0820.vhd(42): signal \"D\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "adc0820.vhd" "" { Text "E:/vhdl code/ad0820new/adc0820.vhd" 42 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "adc0820.vhd(43) " "Info (10425): VHDL Case Statement information at adc0820.vhd(43): OTHERS choice is never selected" {  } { { "adc0820.vhd" "" { Text "E:/vhdl code/ad0820new/adc0820.vhd" 43 0 0 } }  } 0 10425 "VHDL Case Statement information at %1!s!: OTHERS choice is never selected" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "LOCK adc0820.vhd(22) " "Warning (10631): VHDL Process Statement warning at adc0820.vhd(22): signal or variable \"LOCK\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"LOCK\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "adc0820.vhd" "" { Text "E:/vhdl code/ad0820new/adc0820.vhd" 22 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: signal or variable \"%1!s!\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"%1!s!\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." 0 0}