adc0820.tan.qmsg

AD0820小程序

{ "Info" "ITDB_FULL_TCO_RESULT" "clk rd adc0820:inst1\|current_state.st0 11.481 ns register " "Info: tco from clock \"clk\" to destination pin \"rd\" through register \"adc0820:inst1\|current_state.st0\" is 11.481 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.718 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 7.718 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_153 6 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 6; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc0820" "UNKNOWN" "V1" "E:/vhdl code/ad0820new/db/adc0820.quartus_db" { Floorplan "E:/vhdl code/ad0820new/" "" "" { clk } "NODE_NAME" } "" } } { "top.bdf" "" { Schematic "E:/vhdl code/ad0820new/top.bdf" { { 136 -48 120 152 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.030 ns) + CELL(0.935 ns) 3.434 ns div:inst\|clk_tmp 2 REG LC_X8_Y13_N9 13 " "Info: 2: + IC(1.030 ns) + CELL(0.935 ns) = 3.434 ns; Loc. = LC_X8_Y13_N9; Fanout = 13; REG Node = 'div:inst\|clk_tmp'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc0820" "UNKNOWN" "V1" "E:/vhdl code/ad0820new/db/adc0820.quartus_db" { Floorplan "E:/vhdl code/ad0820new/" "" "1.965 ns" { clk div:inst|clk_tmp } "NODE_NAME" } "" } } { "div.vhd" "" { Text "E:/vhdl code/ad0820new/div.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.573 ns) + CELL(0.711 ns) 7.718 ns adc0820:inst1\|current_state.st0 3 REG LC_X2_Y11_N4 2 " "Info: 3: + IC(3.573 ns) + CELL(0.711 ns) = 7.718 ns; Loc. = LC_X2_Y11_N4; Fanout = 2; REG Node = 'adc0820:inst1\|current_state.st0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc0820" "UNKNOWN" "V1" "E:/vhdl code/ad0820new/db/adc0820.quartus_db" { Floorplan "E:/vhdl code/ad0820new/" "" "4.284 ns" { div:inst|clk_tmp adc0820:inst1|current_state.st0 } "NODE_NAME" } "" } } { "adc0820.vhd" "" { Text "E:/vhdl code/ad0820new/adc0820.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 40.36 % ) " "Info: Total cell delay = 3.115 ns ( 40.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.603 ns ( 59.64 % ) " "Info: Total interconnect delay = 4.603 ns ( 59.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc0820" "UNKNOWN" "V1" "E:/vhdl code/ad0820new/db/adc0820.quartus_db" { Floorplan "E:/vhdl code/ad0820new/" "" "7.718 ns" { clk div:inst|clk_tmp adc0820:inst1|current_state.st0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.718 ns" { clk clk~out0 div:inst|clk_tmp adc0820:inst1|current_state.st0 } { 0.000ns 0.000ns 1.030ns 3.573ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "adc0820.vhd" "" { Text "E:/vhdl code/ad0820new/adc0820.vhd" 49 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.539 ns + Longest register pin " "Info: + Longest register to pin delay is 3.539 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns adc0820:inst1\|current_state.st0 1 REG LC_X2_Y11_N4 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y11_N4; Fanout = 2; REG Node = 'adc0820:inst1\|current_state.st0'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc0820" "UNKNOWN" "V1" "E:/vhdl code/ad0820new/db/adc0820.quartus_db" { Floorplan "E:/vhdl code/ad0820new/" "" "" { adc0820:inst1|current_state.st0 } "NODE_NAME" } "" } } { "adc0820.vhd" "" { Text "E:/vhdl code/ad0820new/adc0820.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.415 ns) + CELL(2.124 ns) 3.539 ns rd 2 PIN PIN_39 0 " "Info: 2: + IC(1.415 ns) + CELL(2.124 ns) = 3.539 ns; Loc. = PIN_39; Fanout = 0; PIN Node = 'rd'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc0820" "UNKNOWN" "V1" "E:/vhdl code/ad0820new/db/adc0820.quartus_db" { Floorplan "E:/vhdl code/ad0820new/" "" "3.539 ns" { adc0820:inst1|current_state.st0 rd } "NODE_NAME" } "" } } { "top.bdf" "" { Schematic "E:/vhdl code/ad0820new/top.bdf" { { 80 576 752 96 "rd" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 60.02 % ) " "Info: Total cell delay = 2.124 ns ( 60.02 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.415 ns ( 39.98 % ) " "Info: Total interconnect delay = 1.415 ns ( 39.98 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc0820" "UNKNOWN" "V1" "E:/vhdl code/ad0820new/db/adc0820.quartus_db" { Floorplan "E:/vhdl code/ad0820new/" "" "3.539 ns" { adc0820:inst1|current_state.st0 rd } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.539 ns" { adc0820:inst1|current_state.st0 rd } { 0.000ns 1.415ns } { 0.000ns 2.124ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc0820" "UNKNOWN" "V1" "E:/vhdl code/ad0820new/db/adc0820.quartus_db" { Floorplan "E:/vhdl code/ad0820new/" "" "7.718 ns" { clk div:inst|clk_tmp adc0820:inst1|current_state.st0 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.718 ns" { clk clk~out0 div:inst|clk_tmp adc0820:inst1|current_state.st0 } { 0.000ns 0.000ns 1.030ns 3.573ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc0820" "UNKNOWN" "V1" "E:/vhdl code/ad0820new/db/adc0820.quartus_db" { Floorplan "E:/vhdl code/ad0820new/" "" "3.539 ns" { adc0820:inst1|current_state.st0 rd } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "3.539 ns" { adc0820:inst1|current_state.st0 rd } { 0.000ns 1.415ns } { 0.000ns 2.124ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon May 19 18:11:57 2008 " "Info: Processing ended: Mon May 19 18:11:57 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}