adc0820.tan.qmsg

AD0820小程序

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "adc0820:inst1\|clko " "Info: Detected ripple clock \"adc0820:inst1\|clko\" as buffer" {  } { { "adc0820.vhd" "" { Text "E:/vhdl code/ad0820new/adc0820.vhd" 20 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "adc0820:inst1\|clko" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "div:inst\|clk_tmp " "Info: Detected ripple clock \"div:inst\|clk_tmp\" as buffer" {  } { { "div.vhd" "" { Text "E:/vhdl code/ad0820new/div.vhd" 23 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "div:inst\|clk_tmp" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register adc0820:inst1\|current_state_8 register adc0820:inst1\|current_state.st3 163.32 MHz 6.123 ns Internal " "Info: Clock \"clk\" has Internal fmax of 163.32 MHz between source register \"adc0820:inst1\|current_state_8\" and destination register \"adc0820:inst1\|current_state.st3\" (period= 6.123 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.838 ns + Longest register register " "Info: + Longest register to register delay is 0.838 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns adc0820:inst1\|current_state_8 1 REG LC_X1_Y11_N5 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y11_N5; Fanout = 1; REG Node = 'adc0820:inst1\|current_state_8'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc0820" "UNKNOWN" "V1" "E:/vhdl code/ad0820new/db/adc0820.quartus_db" { Floorplan "E:/vhdl code/ad0820new/" "" "" { adc0820:inst1|current_state_8 } "NODE_NAME" } "" } } { "adc0820.vhd" "" { Text "E:/vhdl code/ad0820new/adc0820.vhd" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.529 ns) + CELL(0.309 ns) 0.838 ns adc0820:inst1\|current_state.st3 2 REG LC_X1_Y11_N1 1 " "Info: 2: + IC(0.529 ns) + CELL(0.309 ns) = 0.838 ns; Loc. = LC_X1_Y11_N1; Fanout = 1; REG Node = 'adc0820:inst1\|current_state.st3'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc0820" "UNKNOWN" "V1" "E:/vhdl code/ad0820new/db/adc0820.quartus_db" { Floorplan "E:/vhdl code/ad0820new/" "" "0.838 ns" { adc0820:inst1|current_state_8 adc0820:inst1|current_state.st3 } "NODE_NAME" } "" } } { "adc0820.vhd" "" { Text "E:/vhdl code/ad0820new/adc0820.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.309 ns ( 36.87 % ) " "Info: Total cell delay = 0.309 ns ( 36.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.529 ns ( 63.13 % ) " "Info: Total interconnect delay = 0.529 ns ( 63.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc0820" "UNKNOWN" "V1" "E:/vhdl code/ad0820new/db/adc0820.quartus_db" { Floorplan "E:/vhdl code/ad0820new/" "" "0.838 ns" { adc0820:inst1|current_state_8 adc0820:inst1|current_state.st3 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "0.838 ns" { adc0820:inst1|current_state_8 adc0820:inst1|current_state.st3 } { 0.000ns 0.529ns } { 0.000ns 0.309ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-5.024 ns - Smallest " "Info: - Smallest clock skew is -5.024 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.718 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 7.718 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_153 6 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 6; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc0820" "UNKNOWN" "V1" "E:/vhdl code/ad0820new/db/adc0820.quartus_db" { Floorplan "E:/vhdl code/ad0820new/" "" "" { clk } "NODE_NAME" } "" } } { "top.bdf" "" { Schematic "E:/vhdl code/ad0820new/top.bdf" { { 136 -48 120 152 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.030 ns) + CELL(0.935 ns) 3.434 ns div:inst\|clk_tmp 2 REG LC_X8_Y13_N9 13 " "Info: 2: + IC(1.030 ns) + CELL(0.935 ns) = 3.434 ns; Loc. = LC_X8_Y13_N9; Fanout = 13; REG Node = 'div:inst\|clk_tmp'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc0820" "UNKNOWN" "V1" "E:/vhdl code/ad0820new/db/adc0820.quartus_db" { Floorplan "E:/vhdl code/ad0820new/" "" "1.965 ns" { clk div:inst|clk_tmp } "NODE_NAME" } "" } } { "div.vhd" "" { Text "E:/vhdl code/ad0820new/div.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.573 ns) + CELL(0.711 ns) 7.718 ns adc0820:inst1\|current_state.st3 3 REG LC_X1_Y11_N1 1 " "Info: 3: + IC(3.573 ns) + CELL(0.711 ns) = 7.718 ns; Loc. = LC_X1_Y11_N1; Fanout = 1; REG Node = 'adc0820:inst1\|current_state.st3'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc0820" "UNKNOWN" "V1" "E:/vhdl code/ad0820new/db/adc0820.quartus_db" { Floorplan "E:/vhdl code/ad0820new/" "" "4.284 ns" { div:inst|clk_tmp adc0820:inst1|current_state.st3 } "NODE_NAME" } "" } } { "adc0820.vhd" "" { Text "E:/vhdl code/ad0820new/adc0820.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 40.36 % ) " "Info: Total cell delay = 3.115 ns ( 40.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.603 ns ( 59.64 % ) " "Info: Total interconnect delay = 4.603 ns ( 59.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc0820" "UNKNOWN" "V1" "E:/vhdl code/ad0820new/db/adc0820.quartus_db" { Floorplan "E:/vhdl code/ad0820new/" "" "7.718 ns" { clk div:inst|clk_tmp adc0820:inst1|current_state.st3 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.718 ns" { clk clk~out0 div:inst|clk_tmp adc0820:inst1|current_state.st3 } { 0.000ns 0.000ns 1.030ns 3.573ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 12.742 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 12.742 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_153 6 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 6; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc0820" "UNKNOWN" "V1" "E:/vhdl code/ad0820new/db/adc0820.quartus_db" { Floorplan "E:/vhdl code/ad0820new/" "" "" { clk } "NODE_NAME" } "" } } { "top.bdf" "" { Schematic "E:/vhdl code/ad0820new/top.bdf" { { 136 -48 120 152 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.030 ns) + CELL(0.935 ns) 3.434 ns div:inst\|clk_tmp 2 REG LC_X8_Y13_N9 13 " "Info: 2: + IC(1.030 ns) + CELL(0.935 ns) = 3.434 ns; Loc. = LC_X8_Y13_N9; Fanout = 13; REG Node = 'div:inst\|clk_tmp'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc0820" "UNKNOWN" "V1" "E:/vhdl code/ad0820new/db/adc0820.quartus_db" { Floorplan "E:/vhdl code/ad0820new/" "" "1.965 ns" { clk div:inst|clk_tmp } "NODE_NAME" } "" } } { "div.vhd" "" { Text "E:/vhdl code/ad0820new/div.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.573 ns) + CELL(0.935 ns) 7.942 ns adc0820:inst1\|clko 3 REG LC_X7_Y12_N2 6 " "Info: 3: + IC(3.573 ns) + CELL(0.935 ns) = 7.942 ns; Loc. = LC_X7_Y12_N2; Fanout = 6; REG Node = 'adc0820:inst1\|clko'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc0820" "UNKNOWN" "V1" "E:/vhdl code/ad0820new/db/adc0820.quartus_db" { Floorplan "E:/vhdl code/ad0820new/" "" "4.508 ns" { div:inst|clk_tmp adc0820:inst1|clko } "NODE_NAME" } "" } } { "adc0820.vhd" "" { Text "E:/vhdl code/ad0820new/adc0820.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.089 ns) + CELL(0.711 ns) 12.742 ns adc0820:inst1\|current_state_8 4 REG LC_X1_Y11_N5 1 " "Info: 4: + IC(4.089 ns) + CELL(0.711 ns) = 12.742 ns; Loc. = LC_X1_Y11_N5; Fanout = 1; REG Node = 'adc0820:inst1\|current_state_8'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc0820" "UNKNOWN" "V1" "E:/vhdl code/ad0820new/db/adc0820.quartus_db" { Floorplan "E:/vhdl code/ad0820new/" "" "4.800 ns" { adc0820:inst1|clko adc0820:inst1|current_state_8 } "NODE_NAME" } "" } } { "adc0820.vhd" "" { Text "E:/vhdl code/ad0820new/adc0820.vhd" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.050 ns ( 31.78 % ) " "Info: Total cell delay = 4.050 ns ( 31.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.692 ns ( 68.22 % ) " "Info: Total interconnect delay = 8.692 ns ( 68.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc0820" "UNKNOWN" "V1" "E:/vhdl code/ad0820new/db/adc0820.quartus_db" { Floorplan "E:/vhdl code/ad0820new/" "" "12.742 ns" { clk div:inst|clk_tmp adc0820:inst1|clko adc0820:inst1|current_state_8 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "12.742 ns" { clk clk~out0 div:inst|clk_tmp adc0820:inst1|clko adc0820:inst1|current_state_8 } { 0.000ns 0.000ns 1.030ns 3.573ns 4.089ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc0820" "UNKNOWN" "V1" "E:/vhdl code/ad0820new/db/adc0820.quartus_db" { Floorplan "E:/vhdl code/ad0820new/" "" "7.718 ns" { clk div:inst|clk_tmp adc0820:inst1|current_state.st3 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.718 ns" { clk clk~out0 div:inst|clk_tmp adc0820:inst1|current_state.st3 } { 0.000ns 0.000ns 1.030ns 3.573ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc0820" "UNKNOWN" "V1" "E:/vhdl code/ad0820new/db/adc0820.quartus_db" { Floorplan "E:/vhdl code/ad0820new/" "" "12.742 ns" { clk div:inst|clk_tmp adc0820:inst1|clko adc0820:inst1|current_state_8 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "12.742 ns" { clk clk~out0 div:inst|clk_tmp adc0820:inst1|clko adc0820:inst1|current_state_8 } { 0.000ns 0.000ns 1.030ns 3.573ns 4.089ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "adc0820.vhd" "" { Text "E:/vhdl code/ad0820new/adc0820.vhd" 52 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "adc0820.vhd" "" { Text "E:/vhdl code/ad0820new/adc0820.vhd" 49 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc0820" "UNKNOWN" "V1" "E:/vhdl code/ad0820new/db/adc0820.quartus_db" { Floorplan "E:/vhdl code/ad0820new/" "" "0.838 ns" { adc0820:inst1|current_state_8 adc0820:inst1|current_state.st3 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "0.838 ns" { adc0820:inst1|current_state_8 adc0820:inst1|current_state.st3 } { 0.000ns 0.529ns } { 0.000ns 0.309ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc0820" "UNKNOWN" "V1" "E:/vhdl code/ad0820new/db/adc0820.quartus_db" { Floorplan "E:/vhdl code/ad0820new/" "" "7.718 ns" { clk div:inst|clk_tmp adc0820:inst1|current_state.st3 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.718 ns" { clk clk~out0 div:inst|clk_tmp adc0820:inst1|current_state.st3 } { 0.000ns 0.000ns 1.030ns 3.573ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc0820" "UNKNOWN" "V1" "E:/vhdl code/ad0820new/db/adc0820.quartus_db" { Floorplan "E:/vhdl code/ad0820new/" "" "12.742 ns" { clk div:inst|clk_tmp adc0820:inst1|clko adc0820:inst1|current_state_8 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "12.742 ns" { clk clk~out0 div:inst|clk_tmp adc0820:inst1|clko adc0820:inst1|current_state_8 } { 0.000ns 0.000ns 1.030ns 3.573ns 4.089ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 6 " "Warning: Circuit may not operate. Detected 6 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "adc0820:inst1\|current_state.st4 adc0820:inst1\|current_state_12 clk 4.157 ns " "Info: Found hold time violation between source  pin or register \"adc0820:inst1\|current_state.st4\" and destination pin or register \"adc0820:inst1\|current_state_12\" for clock \"clk\" (Hold time is 4.157 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "5.024 ns + Largest " "Info: + Largest clock skew is 5.024 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 12.742 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 12.742 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_153 6 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 6; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc0820" "UNKNOWN" "V1" "E:/vhdl code/ad0820new/db/adc0820.quartus_db" { Floorplan "E:/vhdl code/ad0820new/" "" "" { clk } "NODE_NAME" } "" } } { "top.bdf" "" { Schematic "E:/vhdl code/ad0820new/top.bdf" { { 136 -48 120 152 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.030 ns) + CELL(0.935 ns) 3.434 ns div:inst\|clk_tmp 2 REG LC_X8_Y13_N9 13 " "Info: 2: + IC(1.030 ns) + CELL(0.935 ns) = 3.434 ns; Loc. = LC_X8_Y13_N9; Fanout = 13; REG Node = 'div:inst\|clk_tmp'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc0820" "UNKNOWN" "V1" "E:/vhdl code/ad0820new/db/adc0820.quartus_db" { Floorplan "E:/vhdl code/ad0820new/" "" "1.965 ns" { clk div:inst|clk_tmp } "NODE_NAME" } "" } } { "div.vhd" "" { Text "E:/vhdl code/ad0820new/div.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.573 ns) + CELL(0.935 ns) 7.942 ns adc0820:inst1\|clko 3 REG LC_X7_Y12_N2 6 " "Info: 3: + IC(3.573 ns) + CELL(0.935 ns) = 7.942 ns; Loc. = LC_X7_Y12_N2; Fanout = 6; REG Node = 'adc0820:inst1\|clko'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc0820" "UNKNOWN" "V1" "E:/vhdl code/ad0820new/db/adc0820.quartus_db" { Floorplan "E:/vhdl code/ad0820new/" "" "4.508 ns" { div:inst|clk_tmp adc0820:inst1|clko } "NODE_NAME" } "" } } { "adc0820.vhd" "" { Text "E:/vhdl code/ad0820new/adc0820.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.089 ns) + CELL(0.711 ns) 12.742 ns adc0820:inst1\|current_state_12 4 REG LC_X1_Y11_N2 1 " "Info: 4: + IC(4.089 ns) + CELL(0.711 ns) = 12.742 ns; Loc. = LC_X1_Y11_N2; Fanout = 1; REG Node = 'adc0820:inst1\|current_state_12'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc0820" "UNKNOWN" "V1" "E:/vhdl code/ad0820new/db/adc0820.quartus_db" { Floorplan "E:/vhdl code/ad0820new/" "" "4.800 ns" { adc0820:inst1|clko adc0820:inst1|current_state_12 } "NODE_NAME" } "" } } { "adc0820.vhd" "" { Text "E:/vhdl code/ad0820new/adc0820.vhd" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.050 ns ( 31.78 % ) " "Info: Total cell delay = 4.050 ns ( 31.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.692 ns ( 68.22 % ) " "Info: Total interconnect delay = 8.692 ns ( 68.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc0820" "UNKNOWN" "V1" "E:/vhdl code/ad0820new/db/adc0820.quartus_db" { Floorplan "E:/vhdl code/ad0820new/" "" "12.742 ns" { clk div:inst|clk_tmp adc0820:inst1|clko adc0820:inst1|current_state_12 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "12.742 ns" { clk clk~out0 div:inst|clk_tmp adc0820:inst1|clko adc0820:inst1|current_state_12 } { 0.000ns 0.000ns 1.030ns 3.573ns 4.089ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.718 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 7.718 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_153 6 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 6; CLK Node = 'clk'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc0820" "UNKNOWN" "V1" "E:/vhdl code/ad0820new/db/adc0820.quartus_db" { Floorplan "E:/vhdl code/ad0820new/" "" "" { clk } "NODE_NAME" } "" } } { "top.bdf" "" { Schematic "E:/vhdl code/ad0820new/top.bdf" { { 136 -48 120 152 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.030 ns) + CELL(0.935 ns) 3.434 ns div:inst\|clk_tmp 2 REG LC_X8_Y13_N9 13 " "Info: 2: + IC(1.030 ns) + CELL(0.935 ns) = 3.434 ns; Loc. = LC_X8_Y13_N9; Fanout = 13; REG Node = 'div:inst\|clk_tmp'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc0820" "UNKNOWN" "V1" "E:/vhdl code/ad0820new/db/adc0820.quartus_db" { Floorplan "E:/vhdl code/ad0820new/" "" "1.965 ns" { clk div:inst|clk_tmp } "NODE_NAME" } "" } } { "div.vhd" "" { Text "E:/vhdl code/ad0820new/div.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.573 ns) + CELL(0.711 ns) 7.718 ns adc0820:inst1\|current_state.st4 3 REG LC_X1_Y11_N4 1 " "Info: 3: + IC(3.573 ns) + CELL(0.711 ns) = 7.718 ns; Loc. = LC_X1_Y11_N4; Fanout = 1; REG Node = 'adc0820:inst1\|current_state.st4'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc0820" "UNKNOWN" "V1" "E:/vhdl code/ad0820new/db/adc0820.quartus_db" { Floorplan "E:/vhdl code/ad0820new/" "" "4.284 ns" { div:inst|clk_tmp adc0820:inst1|current_state.st4 } "NODE_NAME" } "" } } { "adc0820.vhd" "" { Text "E:/vhdl code/ad0820new/adc0820.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 40.36 % ) " "Info: Total cell delay = 3.115 ns ( 40.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.603 ns ( 59.64 % ) " "Info: Total interconnect delay = 4.603 ns ( 59.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc0820" "UNKNOWN" "V1" "E:/vhdl code/ad0820new/db/adc0820.quartus_db" { Floorplan "E:/vhdl code/ad0820new/" "" "7.718 ns" { clk div:inst|clk_tmp adc0820:inst1|current_state.st4 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.718 ns" { clk clk~out0 div:inst|clk_tmp adc0820:inst1|current_state.st4 } { 0.000ns 0.000ns 1.030ns 3.573ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc0820" "UNKNOWN" "V1" "E:/vhdl code/ad0820new/db/adc0820.quartus_db" { Floorplan "E:/vhdl code/ad0820new/" "" "12.742 ns" { clk div:inst|clk_tmp adc0820:inst1|clko adc0820:inst1|current_state_12 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "12.742 ns" { clk clk~out0 div:inst|clk_tmp adc0820:inst1|clko adc0820:inst1|current_state_12 } { 0.000ns 0.000ns 1.030ns 3.573ns 4.089ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc0820" "UNKNOWN" "V1" "E:/vhdl code/ad0820new/db/adc0820.quartus_db" { Floorplan "E:/vhdl code/ad0820new/" "" "7.718 ns" { clk div:inst|clk_tmp adc0820:inst1|current_state.st4 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.718 ns" { clk clk~out0 div:inst|clk_tmp adc0820:inst1|current_state.st4 } { 0.000ns 0.000ns 1.030ns 3.573ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "adc0820.vhd" "" { Text "E:/vhdl code/ad0820new/adc0820.vhd" 49 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.658 ns - Shortest register register " "Info: - Shortest register to register delay is 0.658 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns adc0820:inst1\|current_state.st4 1 REG LC_X1_Y11_N4 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y11_N4; Fanout = 1; REG Node = 'adc0820:inst1\|current_state.st4'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc0820" "UNKNOWN" "V1" "E:/vhdl code/ad0820new/db/adc0820.quartus_db" { Floorplan "E:/vhdl code/ad0820new/" "" "" { adc0820:inst1|current_state.st4 } "NODE_NAME" } "" } } { "adc0820.vhd" "" { Text "E:/vhdl code/ad0820new/adc0820.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.543 ns) + CELL(0.115 ns) 0.658 ns adc0820:inst1\|current_state_12 2 REG LC_X1_Y11_N2 1 " "Info: 2: + IC(0.543 ns) + CELL(0.115 ns) = 0.658 ns; Loc. = LC_X1_Y11_N2; Fanout = 1; REG Node = 'adc0820:inst1\|current_state_12'" {  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc0820" "UNKNOWN" "V1" "E:/vhdl code/ad0820new/db/adc0820.quartus_db" { Floorplan "E:/vhdl code/ad0820new/" "" "0.658 ns" { adc0820:inst1|current_state.st4 adc0820:inst1|current_state_12 } "NODE_NAME" } "" } } { "adc0820.vhd" "" { Text "E:/vhdl code/ad0820new/adc0820.vhd" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.115 ns ( 17.48 % ) " "Info: Total cell delay = 0.115 ns ( 17.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.543 ns ( 82.52 % ) " "Info: Total interconnect delay = 0.543 ns ( 82.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc0820" "UNKNOWN" "V1" "E:/vhdl code/ad0820new/db/adc0820.quartus_db" { Floorplan "E:/vhdl code/ad0820new/" "" "0.658 ns" { adc0820:inst1|current_state.st4 adc0820:inst1|current_state_12 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "0.658 ns" { adc0820:inst1|current_state.st4 adc0820:inst1|current_state_12 } { 0.000ns 0.543ns } { 0.000ns 0.115ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "adc0820.vhd" "" { Text "E:/vhdl code/ad0820new/adc0820.vhd" 52 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc0820" "UNKNOWN" "V1" "E:/vhdl code/ad0820new/db/adc0820.quartus_db" { Floorplan "E:/vhdl code/ad0820new/" "" "12.742 ns" { clk div:inst|clk_tmp adc0820:inst1|clko adc0820:inst1|current_state_12 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "12.742 ns" { clk clk~out0 div:inst|clk_tmp adc0820:inst1|clko adc0820:inst1|current_state_12 } { 0.000ns 0.000ns 1.030ns 3.573ns 4.089ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc0820" "UNKNOWN" "V1" "E:/vhdl code/ad0820new/db/adc0820.quartus_db" { Floorplan "E:/vhdl code/ad0820new/" "" "7.718 ns" { clk div:inst|clk_tmp adc0820:inst1|current_state.st4 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "7.718 ns" { clk clk~out0 div:inst|clk_tmp adc0820:inst1|current_state.st4 } { 0.000ns 0.000ns 1.030ns 3.573ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "adc0820" "UNKNOWN" "V1" "E:/vhdl code/ad0820new/db/adc0820.quartus_db" { Floorplan "E:/vhdl code/ad0820new/" "" "0.658 ns" { adc0820:inst1|current_state.st4 adc0820:inst1|current_state_12 } "NODE_NAME" } "" } } { "c:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus51/bin/Technology_Viewer.qrui" "0.658 ns" { adc0820:inst1|current_state.st4 adc0820:inst1|current_state_12 } { 0.000ns 0.543ns } { 0.000ns 0.115ns } } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}