top_7279.map.rpt

AD0820小程序

Warning: Reduced register "U7279:inst|FPGA_7279:inst3|cmd_tmp[4]" with stuck data_in port to stuck value VCC
Warning: Reduced register "U7279:inst|FPGA_7279:inst3|cmd_tmp[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "U7279:inst|FPGA_7279:inst3|cmd_tmp1[6]" with stuck data_in port to stuck value GND
Warning: Reduced register "U7279:inst|FPGA_7279:inst3|cmd_tmp1[5]" with stuck data_in port to stuck value GND
Info: Power-up level of register "U7279:inst|FPGA_7279:inst3|cmd_tmp1[4]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "U7279:inst|FPGA_7279:inst3|cmd_tmp1[4]" with stuck data_in port to stuck value VCC
Warning: Reduced register "U7279:inst|FPGA_7279:inst3|cmd_tmp1[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "U7279:inst|FPGA_7279:inst3|data_7279[1][7]" with stuck data_in port to stuck value GND
Warning: Reduced register "U7279:inst|FPGA_7279:inst3|data_7279[2][7]" with stuck data_in port to stuck value GND
Warning: Reduced register "U7279:inst|FPGA_7279:inst3|data_7279[3][7]" with stuck data_in port to stuck value GND
Warning: Reduced register "U7279:inst|FPGA_7279:inst3|data_7279[4][7]" with stuck data_in port to stuck value GND
Warning: Reduced register "U7279:inst|FPGA_7279:inst3|data_7279[5][7]" with stuck data_in port to stuck value GND
Warning: Reduced register "U7279:inst|FPGA_7279:inst3|data_7279[6][7]" with stuck data_in port to stuck value GND
Warning: Reduced register "U7279:inst|FPGA_7279:inst3|data_7279[7][7]" with stuck data_in port to stuck value GND
Warning: Reduced register "U7279:inst|FPGA_7279:inst3|data_7279[0][7]" with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
    Info: Duplicate register "U7279:inst|div:inst|clk_tmp" merged to single register "div:inst2|clk_tmp"
Warning: Reduced register "U7279:inst|FPGA_7279:inst3|data_tmp[7]" with stuck data_in port to stuck value GND
Warning: Reduced register "U7279:inst|FPGA_7279:inst3|data_tmp1[7]" with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
    Info: Duplicate register "KEYVALUE:inst1|Q[20]" merged to single register "KEYVALUE:inst1|Q[31]"
    Info: Duplicate register "KEYVALUE:inst1|Q[17]" merged to single register "KEYVALUE:inst1|Q[31]"
    Info: Duplicate register "KEYVALUE:inst1|Q[13]" merged to single register "KEYVALUE:inst1|Q[31]"
    Info: Duplicate register "KEYVALUE:inst1|Q[29]" merged to single register "KEYVALUE:inst1|Q[31]"
    Info: Duplicate register "KEYVALUE:inst1|Q[12]" merged to single register "KEYVALUE:inst1|Q[31]"
    Info: Duplicate register "KEYVALUE:inst1|Q[10]" merged to single register "KEYVALUE:inst1|Q[31]"
    Info: Duplicate register "KEYVALUE:inst1|Q[7]" merged to single register "KEYVALUE:inst1|Q[31]"
    Info: Duplicate register "KEYVALUE:inst1|Q[24]" merged to single register "KEYVALUE:inst1|Q[30]"
    Info: Duplicate register "KEYVALUE:inst1|Q[18]" merged to single register "KEYVALUE:inst1|Q[30]"
    Info: Duplicate register "KEYVALUE:inst1|Q[4]" merged to single register "KEYVALUE:inst1|Q[30]"
    Info: Duplicate register "KEYVALUE:inst1|Q[0]" merged to single register "KEYVALUE:inst1|Q[30]"
    Info: Duplicate register "KEYVALUE:inst1|Q[15]" merged to single register "KEYVALUE:inst1|Q[30]"
    Info: Duplicate register "KEYVALUE:inst1|Q[25]" merged to single register "KEYVALUE:inst1|Q[30]"
    Info: Duplicate register "KEYVALUE:inst1|Q[8]" merged to single register "KEYVALUE:inst1|Q[30]"
    Info: Duplicate register "KEYVALUE:inst1|Q[14]" merged to single register "KEYVALUE:inst1|Q[30]"
    Info: Duplicate register "KEYVALUE:inst1|Q[11]" merged to single register "KEYVALUE:inst1|Q[30]"
    Info: Duplicate register "KEYVALUE:inst1|Q[21]" merged to single register "KEYVALUE:inst1|Q[30]"
    Info: Duplicate register "KEYVALUE:inst1|Q[3]" merged to single register "KEYVALUE:inst1|Q[30]"
    Info: Duplicate register "KEYVALUE:inst1|Q[1]" merged to single register "KEYVALUE:inst1|Q[30]"
    Info: Duplicate register "KEYVALUE:inst1|Q[9]" merged to single register "KEYVALUE:inst1|Q[30]"
    Info: Duplicate register "KEYVALUE:inst1|Q[26]" merged to single register "KEYVALUE:inst1|Q[30]"
    Info: Duplicate register "KEYVALUE:inst1|Q[23]" merged to single register "KEYVALUE:inst1|Q[30]"
    Info: Duplicate register "KEYVALUE:inst1|Q[5]" merged to single register "KEYVALUE:inst1|Q[30]"
    Info: Duplicate register "KEYVALUE:inst1|Q[27]" merged to single register "KEYVALUE:inst1|Q[30]"
    Info: Duplicate register "KEYVALUE:inst1|Q[22]" merged to single register "KEYVALUE:inst1|Q[30]"
    Info: Duplicate register "KEYVALUE:inst1|Q[6]" merged to single register "KEYVALUE:inst1|Q[30]"
    Info: Duplicate register "KEYVALUE:inst1|Q[16]" merged to single register "KEYVALUE:inst1|Q[28]"
    Info: Duplicate register "KEYVALUE:inst1|Q[19]" merged to single register "KEYVALUE:inst1|Q[28]"
Info: Power-up level of register "KEYVALUE:inst1|Q[31]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "KEYVALUE:inst1|Q[31]" with stuck data_in port to stuck value VCC
Warning: Reduced register "KEYVALUE:inst1|Q[30]" with stuck data_in port to stuck value GND
Info: State machine "|top|KEYVALUE:inst1|state_ky" contains 3 states
Info: State machine "|top|U7279:inst|Display8:inst5|state" contains 7 states
Info: State machine "|top|U7279:inst|FPGA_7279:inst3|state" contains 12 states
Info: State machine "|top|U7279:inst|FPGA_7279:inst3|state1" contains 3 states
Info: Selected Auto state machine encoding method for state machine "|top|KEYVALUE:inst1|state_ky"
Info: Encoding result for state machine "|top|KEYVALUE:inst1|state_ky"
    Info: Completed encoding using 3 state bits
        Info: Encoded state bit "KEYVALUE:inst1|state_ky.stop"
        Info: Encoded state bit "KEYVALUE:inst1|state_ky.start"
        Info: Encoded state bit "KEYVALUE:inst1|state_ky.idle"
    Info: State "|top|KEYVALUE:inst1|state_ky.idle" uses code string "000"
    Info: State "|top|KEYVALUE:inst1|state_ky.start" uses code string "011"
    Info: State "|top|KEYVALUE:inst1|state_ky.stop" uses code string "101"
Info: Selected Auto state machine encoding method for state machine "|top|U7279:inst|Display8:inst5|state"
Info: Encoding result for state machine "|top|U7279:inst|Display8:inst5|state"
    Info: Completed encoding using 7 state bits
        Info: Encoded state bit "U7279:inst|Display8:inst5|state.wr_stop"
        Info: Encoded state bit "U7279:inst|Display8:inst5|state.d_hold"
        Info: Encoded state bit "U7279:inst|Display8:inst5|state.d_write"
        Info: Encoded state bit "U7279:inst|Display8:inst5|state.d_setup1"
        Info: Encoded state bit "U7279:inst|Display8:inst5|state.d_setup"
        Info: Encoded state bit "U7279:inst|Display8:inst5|state.start"
        Info: Encoded state bit "U7279:inst|Display8:inst5|state.idle"
    Info: State "|top|U7279:inst|Display8:inst5|state.idle" uses code string "0000000"
    Info: State "|top|U7279:inst|Display8:inst5|state.start" uses code string "0000011"
    Info: State "|top|U7279:inst|Display8:inst5|state.d_setup" uses code string "0000101"
    Info: State "|top|U7279:inst|Display8:inst5|state.d_setup1" uses code string "0001001"
    Info: State "|top|U7279:inst|Display8:inst5|state.d_write" uses code string "0010001"
    Info: State "|top|U7279:inst|Display8:inst5|state.d_hold" uses code string "0100001"
    Info: State "|top|U7279:inst|Display8:inst5|state.wr_stop" uses code string "1000001"
Info: Selected Auto state machine encoding method for state machine "|top|U7279:inst|FPGA_7279:inst3|state"
Info: Encoding result for state machine "|top|U7279:inst|FPGA_7279:inst3|state"
    Info: Completed encoding using 12 state bits
        Info: Encoded state bit "U7279:inst|FPGA_7279:inst3|state.finish"
        Info: Encoded state bit "U7279:inst|FPGA_7279:inst3|state.shift_key_high1"
        Info: Encoded state bit "U7279:inst|FPGA_7279:inst3|state.shift_key_high"
        Info: Encoded state bit "U7279:inst|FPGA_7279:inst3|state.shift_key_low"
        Info: Encoded state bit "U7279:inst|FPGA_7279:inst3|state.shift_data_high"
        Info: Encoded state bit "U7279:inst|FPGA_7279:inst3|state.shift_data_low"
        Info: Encoded state bit "U7279:inst|FPGA_7279:inst3|state.next_delay"
        Info: Encoded state bit "U7279:inst|FPGA_7279:inst3|state.shift_cmd_high"
        Info: Encoded state bit "U7279:inst|FPGA_7279:inst3|state.shift_cmd_low"
        Info: Encoded state bit "U7279:inst|FPGA_7279:inst3|state.start_delay"
        Info: Encoded state bit "U7279:inst|FPGA_7279:inst3|state.start"
        Info: Encoded state bit "U7279:inst|FPGA_7279:inst3|state.idle"
    Info: State "|top|U7279:inst|FPGA_7279:inst3|state.idle" uses code string "000000000000"
    Info: State "|top|U7279:inst|FPGA_7279:inst3|state.start" uses code string "000000000011"
    Info: State "|top|U7279:inst|FPGA_7279:inst3|state.start_delay" uses code string "000000000101"
    Info: State "|top|U7279:inst|FPGA_7279:inst3|state.shift_cmd_low" uses code string "000000001001"
    Info: State "|top|U7279:inst|FPGA_7279:inst3|state.shift_cmd_high" uses code string "000000010001"
    Info: State "|top|U7279:inst|FPGA_7279:inst3|state.next_delay" uses code string "000000100001"
    Info: State "|top|U7279:inst|FPGA_7279:inst3|state.shift_data_low" uses code string "000001000001"
    Info: State "|top|U7279:inst|FPGA_7279:inst3|state.shift_data_high" uses code string "000010000001"
    Info: State "|top|U7279:inst|FPGA_7279:inst3|state.shift_key_low" uses code string "000100000001"
    Info: State "|top|U7279:inst|FPGA_7279:inst3|state.shift_key_high" uses code string "001000000001"
    Info: State "|top|U7279:inst|FPGA_7279:inst3|state.shift_key_high1" uses code string "010000000001"
    Info: State "|top|U7279:inst|FPGA_7279:inst3|state.finish" uses code string "100000000001"
Info: Selected Auto state machine encoding method for state machine "|top|U7279:inst|FPGA_7279:inst3|state1"
Info: Encoding result for state machine "|top|U7279:inst|FPGA_7279:inst3|state1"
    Info: Completed encoding using 3 state bits
        Info: Encoded state bit "U7279:inst|FPGA_7279:inst3|state1.stop"
        Info: Encoded state bit "U7279:inst|FPGA_7279:inst3|state1.start_wr"
        Info: Encoded state bit "U7279:inst|FPGA_7279:inst3|state1.idle"
    Info: State "|top|U7279:inst|FPGA_7279:inst3|state1.idle" uses code string "000"
    Info: State "|top|U7279:inst|FPGA_7279:inst3|state1.start_wr" uses code string "011"
    Info: State "|top|U7279:inst|FPGA_7279:inst3|state1.stop" uses code string "101"
Info: Registers with preset signals will power-up high
Info: Implemented 270 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 2 output pins
    Info: Implemented 1 bidirectional pins
    Info: Implemented 264 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 35 warnings
    Info: Processing ended: Sat May 17 23:09:46 2008
    Info: Elapsed time: 00:00:09