top_7279.map.rpt

AD0820小程序

+----------------------------------------------+-------+


+---------------------------------------------------+
; Inverted Register Statistics                      ;
+-----------------------------------------+---------+
; Inverted Register                       ; Fan out ;
+-----------------------------------------+---------+
; U7279:inst|FPGA_7279:inst3|CS7279       ; 2       ;
; U7279:inst|Display8:inst5|WR_N          ; 5       ;
; KEYVALUE:inst1|key_7279[0]              ; 3       ;
; KEYVALUE:inst1|key_7279[1]              ; 3       ;
; KEYVALUE:inst1|key_7279[2]              ; 1       ;
; KEYVALUE:inst1|key_7279[3]              ; 1       ;
; KEYVALUE:inst1|key_7279[4]              ; 1       ;
; KEYVALUE:inst1|key_7279[5]              ; 1       ;
; KEYVALUE:inst1|key_7279[7]              ; 1       ;
; KEYVALUE:inst1|key_7279[6]              ; 1       ;
; Total number of inverted registers = 10 ;         ;
+-----------------------------------------+---------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                              ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                    ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------+
; 8:1                ; 7 bits    ; 35 LEs        ; 35 LEs               ; 0 LEs                  ; Yes        ; |top|U7279:inst|FPGA_7279:inst3|data_tmp[0]   ;
; 5:1                ; 3 bits    ; 9 LEs         ; 3 LEs                ; 6 LEs                  ; Yes        ; |top|U7279:inst|FPGA_7279:inst3|scmd_cnt[0]   ;
; 5:1                ; 3 bits    ; 9 LEs         ; 3 LEs                ; 6 LEs                  ; Yes        ; |top|U7279:inst|FPGA_7279:inst3|sdata_cnt[2]  ;
; 7:1                ; 2 bits    ; 8 LEs         ; 2 LEs                ; 6 LEs                  ; Yes        ; |top|U7279:inst|FPGA_7279:inst3|delay_cnt[1]  ;
; 256:1              ; 4 bits    ; 680 LEs       ; 8 LEs                ; 672 LEs                ; Yes        ; |top|KEYVALUE:inst1|Q[2]                      ;
; 8:1                ; 2 bits    ; 10 LEs        ; 8 LEs                ; 2 LEs                  ; No         ; |top|U7279:inst|FPGA_7279:inst3|decode_bus~95 ;
; 9:1                ; 2 bits    ; 12 LEs        ; 12 LEs               ; 0 LEs                  ; No         ; |top|U7279:inst|FPGA_7279:inst3|decode_bus~98 ;
; 14:1               ; 2 bits    ; 18 LEs        ; 18 LEs               ; 0 LEs                  ; No         ; |top|U7279:inst|FPGA_7279:inst3|decode_bus~99 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------+


+------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: U7279:inst|div:inst ;
+----------------+-------+-----------------------------------------+
; Parameter Name ; Value ; Type                                    ;
+----------------+-------+-----------------------------------------+
; div_nx2        ; 10    ; Untyped                                 ;
+----------------+-------+-----------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: U7279:inst|div:inst1 ;
+----------------+-------+------------------------------------------+
; Parameter Name ; Value ; Type                                     ;
+----------------+-------+------------------------------------------+
; div_nx2        ; 400   ; Untyped                                  ;
+----------------+-------+------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------+
; Parameter Settings for User Entity Instance: div:inst2 ;
+----------------+-------+-------------------------------+
; Parameter Name ; Value ; Type                          ;
+----------------+-------+-------------------------------+
; div_nx2        ; 10    ; Untyped                       ;
+----------------+-------+-------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/vhdl code/HD7279/top_7279.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Sat May 17 23:09:37 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off top_7279 -c top_7279
Info: Found 2 design units, including 1 entities, in source file Display8.vhd
    Info: Found design unit 1: Display8-one
    Info: Found entity 1: Display8
Info: Found 2 design units, including 1 entities, in source file DIV.vhd
    Info: Found design unit 1: div-behav
    Info: Found entity 1: div
Info: Found 2 design units, including 1 entities, in source file FPGA_7279.vhd
    Info: Found design unit 1: FPGA_7279-behav
    Info: Found entity 1: FPGA_7279
Warning: Can't analyze file -- file E:/vhdl code/HD7279/AA.vhd is missing
Info: Found 2 design units, including 1 entities, in source file KEYVALUE.vhd
    Info: Found design unit 1: KEYVALUE-a
    Info: Found entity 1: KEYVALUE
Info: Found 1 design units, including 1 entities, in source file U7279.bdf
    Info: Found entity 1: U7279
Info: Found 1 design units, including 1 entities, in source file top.bdf
    Info: Found entity 1: top
Info: Elaborating entity "top" for the top level hierarchy
Info: Elaborating entity "U7279" for hierarchy "U7279:inst"
Info: Elaborating entity "FPGA_7279" for hierarchy "U7279:inst|FPGA_7279:inst3"
Info (10035): Verilog HDL or VHDL information at FPGA_7279.vhd(47): object "cmd_7279" declared but not used
Info (10035): Verilog HDL or VHDL information at FPGA_7279.vhd(59): object "f_edge_cnt" declared but not used
Warning (10036): Verilog HDL or VHDL warning at FPGA_7279.vhd(64): object "cmd_start_tmp" assigned a value but never read
Info (10035): Verilog HDL or VHDL information at FPGA_7279.vhd(68): object "seg_r" declared but not used
Info (10425): VHDL Case Statement information at FPGA_7279.vhd(188): OTHERS choice is never selected
Warning (10492): VHDL Process Statement warning at FPGA_7279.vhd(226): signal "RD_N" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info (10425): VHDL Case Statement information at FPGA_7279.vhd(276): OTHERS choice is never selected
Info: Elaborating entity "Display8" for hierarchy "U7279:inst|Display8:inst5"
Warning (10492): VHDL Process Statement warning at Display8.vhd(27): signal "Din" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at Display8.vhd(28): signal "Din" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at Display8.vhd(29): signal "Din" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at Display8.vhd(30): signal "Din" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at Display8.vhd(31): signal "Din" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at Display8.vhd(32): signal "Din" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at Display8.vhd(33): signal "Din" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at Display8.vhd(34): signal "Din" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info (10425): VHDL Case Statement information at Display8.vhd(35): OTHERS choice is never selected
Info: Elaborating entity "div" for hierarchy "U7279:inst|div:inst"
Info: Elaborating entity "div" for hierarchy "U7279:inst|div:inst1"
Info: Elaborating entity "KEYVALUE" for hierarchy "KEYVALUE:inst1"
Info (10425): VHDL Case Statement information at KEYVALUE.vhd(41): OTHERS choice is never selected
Warning: Reduced register "U7279:inst|Display8:inst5|D_BUS[7]" with stuck data_in port to stuck value GND
Warning: Reduced register "U7279:inst|Display8:inst5|D_BUS[6]" with stuck data_in port to stuck value GND
Warning: Reduced register "U7279:inst|Display8:inst5|D_BUS[5]" with stuck data_in port to stuck value GND
Warning: Reduced register "U7279:inst|Display8:inst5|D_BUS[4]" with stuck data_in port to stuck value GND
Warning: Reduced register "U7279:inst|FPGA_7279:inst3|cmd_tmp[6]" with stuck data_in port to stuck value GND
Warning: Reduced register "U7279:inst|FPGA_7279:inst3|cmd_tmp[5]" with stuck data_in port to stuck value GND
Info: Power-up level of register "U7279:inst|FPGA_7279:inst3|cmd_tmp[4]" is not specified -- using power-up level of High to minimize register