top_7279.map.qmsg

AD0820小程序

{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "KEYVALUE:inst1\|Q\[31\] High " "Info: Power-up level of register \"KEYVALUE:inst1\|Q\[31\]\" is not specified -- using power-up level of High to minimize register" {  } { { "KEYVALUE.vhd" "" { Text "E:/vhdl code/HD7279/KEYVALUE.vhd" 49 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "KEYVALUE:inst1\|Q\[31\] data_in VCC " "Warning: Reduced register \"KEYVALUE:inst1\|Q\[31\]\" with stuck data_in port to stuck value VCC" {  } { { "KEYVALUE.vhd" "" { Text "E:/vhdl code/HD7279/KEYVALUE.vhd" 49 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "KEYVALUE:inst1\|Q\[30\] data_in GND " "Warning: Reduced register \"KEYVALUE:inst1\|Q\[30\]\" with stuck data_in port to stuck value GND" {  } { { "KEYVALUE.vhd" "" { Text "E:/vhdl code/HD7279/KEYVALUE.vhd" 49 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|top\|KEYVALUE:inst1\|state_ky 3 " "Info: State machine \"\|top\|KEYVALUE:inst1\|state_ky\" contains 3 states" {  } { { "KEYVALUE.vhd" "" { Text "E:/vhdl code/HD7279/KEYVALUE.vhd" 20 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|top\|U7279:inst\|Display8:inst5\|state 7 " "Info: State machine \"\|top\|U7279:inst\|Display8:inst5\|state\" contains 7 states" {  } { { "Display8.vhd" "" { Text "E:/vhdl code/HD7279/Display8.vhd" 21 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|top\|U7279:inst\|FPGA_7279:inst3\|state 12 " "Info: State machine \"\|top\|U7279:inst\|FPGA_7279:inst3\|state\" contains 12 states" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 74 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|top\|U7279:inst\|FPGA_7279:inst3\|state1 3 " "Info: State machine \"\|top\|U7279:inst\|FPGA_7279:inst3\|state1\" contains 3 states" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 76 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|top\|KEYVALUE:inst1\|state_ky " "Info: Selected Auto state machine encoding method for state machine \"\|top\|KEYVALUE:inst1\|state_ky\"" {  } { { "KEYVALUE.vhd" "" { Text "E:/vhdl code/HD7279/KEYVALUE.vhd" 20 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|top\|KEYVALUE:inst1\|state_ky " "Info: Encoding result for state machine \"\|top\|KEYVALUE:inst1\|state_ky\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "3 " "Info: Completed encoding using 3 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "KEYVALUE:inst1\|state_ky.stop " "Info: Encoded state bit \"KEYVALUE:inst1\|state_ky.stop\"" {  } { { "KEYVALUE.vhd" "" { Text "E:/vhdl code/HD7279/KEYVALUE.vhd" 24 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "KEYVALUE:inst1\|state_ky.start " "Info: Encoded state bit \"KEYVALUE:inst1\|state_ky.start\"" {  } { { "KEYVALUE.vhd" "" { Text "E:/vhdl code/HD7279/KEYVALUE.vhd" 24 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "KEYVALUE:inst1\|state_ky.idle " "Info: Encoded state bit \"KEYVALUE:inst1\|state_ky.idle\"" {  } { { "KEYVALUE.vhd" "" { Text "E:/vhdl code/HD7279/KEYVALUE.vhd" 24 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|top\|KEYVALUE:inst1\|state_ky.idle 000 " "Info: State \"\|top\|KEYVALUE:inst1\|state_ky.idle\" uses code string \"000\"" {  } { { "KEYVALUE.vhd" "" { Text "E:/vhdl code/HD7279/KEYVALUE.vhd" 24 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|top\|KEYVALUE:inst1\|state_ky.start 011 " "Info: State \"\|top\|KEYVALUE:inst1\|state_ky.start\" uses code string \"011\"" {  } { { "KEYVALUE.vhd" "" { Text "E:/vhdl code/HD7279/KEYVALUE.vhd" 24 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|top\|KEYVALUE:inst1\|state_ky.stop 101 " "Info: State \"\|top\|KEYVALUE:inst1\|state_ky.stop\" uses code string \"101\"" {  } { { "KEYVALUE.vhd" "" { Text "E:/vhdl code/HD7279/KEYVALUE.vhd" 24 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "KEYVALUE.vhd" "" { Text "E:/vhdl code/HD7279/KEYVALUE.vhd" 20 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|top\|U7279:inst\|Display8:inst5\|state " "Info: Selected Auto state machine encoding method for state machine \"\|top\|U7279:inst\|Display8:inst5\|state\"" {  } { { "Display8.vhd" "" { Text "E:/vhdl code/HD7279/Display8.vhd" 21 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|top\|U7279:inst\|Display8:inst5\|state " "Info: Encoding result for state machine \"\|top\|U7279:inst\|Display8:inst5\|state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "7 " "Info: Completed encoding using 7 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "U7279:inst\|Display8:inst5\|state.wr_stop " "Info: Encoded state bit \"U7279:inst\|Display8:inst5\|state.wr_stop\"" {  } { { "Display8.vhd" "" { Text "E:/vhdl code/HD7279/Display8.vhd" 42 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "U7279:inst\|Display8:inst5\|state.d_hold " "Info: Encoded state bit \"U7279:inst\|Display8:inst5\|state.d_hold\"" {  } { { "Display8.vhd" "" { Text "E:/vhdl code/HD7279/Display8.vhd" 42 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "U7279:inst\|Display8:inst5\|state.d_write " "Info: Encoded state bit \"U7279:inst\|Display8:inst5\|state.d_write\"" {  } { { "Display8.vhd" "" { Text "E:/vhdl code/HD7279/Display8.vhd" 42 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "U7279:inst\|Display8:inst5\|state.d_setup1 " "Info: Encoded state bit \"U7279:inst\|Display8:inst5\|state.d_setup1\"" {  } { { "Display8.vhd" "" { Text "E:/vhdl code/HD7279/Display8.vhd" 42 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "U7279:inst\|Display8:inst5\|state.d_setup " "Info: Encoded state bit \"U7279:inst\|Display8:inst5\|state.d_setup\"" {  } { { "Display8.vhd" "" { Text "E:/vhdl code/HD7279/Display8.vhd" 42 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "U7279:inst\|Display8:inst5\|state.start " "Info: Encoded state bit \"U7279:inst\|Display8:inst5\|state.start\"" {  } { { "Display8.vhd" "" { Text "E:/vhdl code/HD7279/Display8.vhd" 42 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "U7279:inst\|Display8:inst5\|state.idle " "Info: Encoded state bit \"U7279:inst\|Display8:inst5\|state.idle\"" {  } { { "Display8.vhd" "" { Text "E:/vhdl code/HD7279/Display8.vhd" 42 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|top\|U7279:inst\|Display8:inst5\|state.idle 0000000 " "Info: State \"\|top\|U7279:inst\|Display8:inst5\|state.idle\" uses code string \"0000000\"" {  } { { "Display8.vhd" "" { Text "E:/vhdl code/HD7279/Display8.vhd" 42 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|top\|U7279:inst\|Display8:inst5\|state.start 0000011 " "Info: State \"\|top\|U7279:inst\|Display8:inst5\|state.start\" uses code string \"0000011\"" {  } { { "Display8.vhd" "" { Text "E:/vhdl code/HD7279/Display8.vhd" 42 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|top\|U7279:inst\|Display8:inst5\|state.d_setup 0000101 " "Info: State \"\|top\|U7279:inst\|Display8:inst5\|state.d_setup\" uses code string \"0000101\"" {  } { { "Display8.vhd" "" { Text "E:/vhdl code/HD7279/Display8.vhd" 42 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|top\|U7279:inst\|Display8:inst5\|state.d_setup1 0001001 " "Info: State \"\|top\|U7279:inst\|Display8:inst5\|state.d_setup1\" uses code string \"0001001\"" {  } { { "Display8.vhd" "" { Text "E:/vhdl code/HD7279/Display8.vhd" 42 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|top\|U7279:inst\|Display8:inst5\|state.d_write 0010001 " "Info: State \"\|top\|U7279:inst\|Display8:inst5\|state.d_write\" uses code string \"0010001\"" {  } { { "Display8.vhd" "" { Text "E:/vhdl code/HD7279/Display8.vhd" 42 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|top\|U7279:inst\|Display8:inst5\|state.d_hold 0100001 " "Info: State \"\|top\|U7279:inst\|Display8:inst5\|state.d_hold\" uses code string \"0100001\"" {  } { { "Display8.vhd" "" { Text "E:/vhdl code/HD7279/Display8.vhd" 42 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|top\|U7279:inst\|Display8:inst5\|state.wr_stop 1000001 " "Info: State \"\|top\|U7279:inst\|Display8:inst5\|state.wr_stop\" uses code string \"1000001\"" {  } { { "Display8.vhd" "" { Text "E:/vhdl code/HD7279/Display8.vhd" 42 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "Display8.vhd" "" { Text "E:/vhdl code/HD7279/Display8.vhd" 21 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|top\|U7279:inst\|FPGA_7279:inst3\|state " "Info: Selected Auto state machine encoding method for state machine \"\|top\|U7279:inst\|FPGA_7279:inst3\|state\"" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 74 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|top\|U7279:inst\|FPGA_7279:inst3\|state " "Info: Encoding result for state machine \"\|top\|U7279:inst\|FPGA_7279:inst3\|state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "12 " "Info: Completed encoding using 12 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "U7279:inst\|FPGA_7279:inst3\|state.finish " "Info: Encoded state bit \"U7279:inst\|FPGA_7279:inst3\|state.finish\"" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "U7279:inst\|FPGA_7279:inst3\|state.shift_key_high1 " "Info: Encoded state bit \"U7279:inst\|FPGA_7279:inst3\|state.shift_key_high1\"" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "U7279:inst\|FPGA_7279:inst3\|state.shift_key_high " "Info: Encoded state bit \"U7279:inst\|FPGA_7279:inst3\|state.shift_key_high\"" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "U7279:inst\|FPGA_7279:inst3\|state.shift_key_low " "Info: Encoded state bit \"U7279:inst\|FPGA_7279:inst3\|state.shift_key_low\"" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "U7279:inst\|FPGA_7279:inst3\|state.shift_data_high " "Info: Encoded state bit \"U7279:inst\|FPGA_7279:inst3\|state.shift_data_high\"" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "U7279:inst\|FPGA_7279:inst3\|state.shift_data_low " "Info: Encoded state bit \"U7279:inst\|FPGA_7279:inst3\|state.shift_data_low\"" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "U7279:inst\|FPGA_7279:inst3\|state.next_delay " "Info: Encoded state bit \"U7279:inst\|FPGA_7279:inst3\|state.next_delay\"" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "U7279:inst\|FPGA_7279:inst3\|state.shift_cmd_high " "Info: Encoded state bit \"U7279:inst\|FPGA_7279:inst3\|state.shift_cmd_high\"" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "U7279:inst\|FPGA_7279:inst3\|state.shift_cmd_low " "Info: Encoded state bit \"U7279:inst\|FPGA_7279:inst3\|state.shift_cmd_low\"" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "U7279:inst\|FPGA_7279:inst3\|state.start_delay " "Info: Encoded state bit \"U7279:inst\|FPGA_7279:inst3\|state.start_delay\"" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "U7279:inst\|FPGA_7279:inst3\|state.start " "Info: Encoded state bit \"U7279:inst\|FPGA_7279:inst3\|state.start\"" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "U7279:inst\|FPGA_7279:inst3\|state.idle " "Info: Encoded state bit \"U7279:inst\|FPGA_7279:inst3\|state.idle\"" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|top\|U7279:inst\|FPGA_7279:inst3\|state.idle 000000000000 " "Info: State \"\|top\|U7279:inst\|FPGA_7279:inst3\|state.idle\" uses code string \"000000000000\"" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|top\|U7279:inst\|FPGA_7279:inst3\|state.start 000000000011 " "Info: State \"\|top\|U7279:inst\|FPGA_7279:inst3\|state.start\" uses code string \"000000000011\"" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|top\|U7279:inst\|FPGA_7279:inst3\|state.start_delay 000000000101 " "Info: State \"\|top\|U7279:inst\|FPGA_7279:inst3\|state.start_delay\" uses code string \"000000000101\"" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|top\|U7279:inst\|FPGA_7279:inst3\|state.shift_cmd_low 000000001001 " "Info: State \"\|top\|U7279:inst\|FPGA_7279:inst3\|state.shift_cmd_low\" uses code string \"000000001001\"" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|top\|U7279:inst\|FPGA_7279:inst3\|state.shift_cmd_high 000000010001 " "Info: State \"\|top\|U7279:inst\|FPGA_7279:inst3\|state.shift_cmd_high\" uses code string \"000000010001\"" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|top\|U7279:inst\|FPGA_7279:inst3\|state.next_delay 000000100001 " "Info: State \"\|top\|U7279:inst\|FPGA_7279:inst3\|state.next_delay\" uses code string \"000000100001\"" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|top\|U7279:inst\|FPGA_7279:inst3\|state.shift_data_low 000001000001 " "Info: State \"\|top\|U7279:inst\|FPGA_7279:inst3\|state.shift_data_low\" uses code string \"000001000001\"" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|top\|U7279:inst\|FPGA_7279:inst3\|state.shift_data_high 000010000001 " "Info: State \"\|top\|U7279:inst\|FPGA_7279:inst3\|state.shift_data_high\" uses code string \"000010000001\"" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|top\|U7279:inst\|FPGA_7279:inst3\|state.shift_key_low 000100000001 " "Info: State \"\|top\|U7279:inst\|FPGA_7279:inst3\|state.shift_key_low\" uses code string \"000100000001\"" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|top\|U7279:inst\|FPGA_7279:inst3\|state.shift_key_high 001000000001 " "Info: State \"\|top\|U7279:inst\|FPGA_7279:inst3\|state.shift_key_high\" uses code string \"001000000001\"" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|top\|U7279:inst\|FPGA_7279:inst3\|state.shift_key_high1 010000000001 " "Info: State \"\|top\|U7279:inst\|FPGA_7279:inst3\|state.shift_key_high1\" uses code string \"010000000001\"" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|top\|U7279:inst\|FPGA_7279:inst3\|state.finish 100000000001 " "Info: State \"\|top\|U7279:inst\|FPGA_7279:inst3\|state.finish\" uses code string \"100000000001\"" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 74 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|top\|U7279:inst\|FPGA_7279:inst3\|state1 " "Info: Selected Auto state machine encoding method for state machine \"\|top\|U7279:inst\|FPGA_7279:inst3\|state1\"" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 76 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|top\|U7279:inst\|FPGA_7279:inst3\|state1 " "Info: Encoding result for state machine \"\|top\|U7279:inst\|FPGA_7279:inst3\|state1\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "3 " "Info: Completed encoding using 3 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "U7279:inst\|FPGA_7279:inst3\|state1.stop " "Info: Encoded state bit \"U7279:inst\|FPGA_7279:inst3\|state1.stop\"" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 256 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "U7279:inst\|FPGA_7279:inst3\|state1.start_wr " "Info: Encoded state bit \"U7279:inst\|FPGA_7279:inst3\|state1.start_wr\"" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 256 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "U7279:inst\|FPGA_7279:inst3\|state1.idle " "Info: Encoded state bit \"U7279:inst\|FPGA_7279:inst3\|state1.idle\"" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 256 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|top\|U7279:inst\|FPGA_7279:inst3\|state1.idle 000 " "Info: State \"\|top\|U7279:inst\|FPGA_7279:inst3\|state1.idle\" uses code string \"000\"" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 256 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|top\|U7279:inst\|FPGA_7279:inst3\|state1.start_wr 011 " "Info: State \"\|top\|U7279:inst\|FPGA_7279:inst3\|state1.start_wr\" uses code string \"011\"" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 256 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|top\|U7279:inst\|FPGA_7279:inst3\|state1.stop 101 " "Info: State \"\|top\|U7279:inst\|FPGA_7279:inst3\|state1.stop\" uses code string \"101\"" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 256 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 76 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 24 -1 0 } } { "Display8.vhd" "" { Text "E:/vhdl code/HD7279/Display8.vhd" 9 -1 0 } } { "KEYVALUE.vhd" "" { Text "E:/vhdl code/HD7279/KEYVALUE.vhd" 24 -1 0 } } { "KEYVALUE.vhd" "" { Text "E:/vhdl code/HD7279/KEYVALUE.vhd" 24 -1 0 } } { "KEYVALUE.vhd" "" { Text "E:/vhdl code/HD7279/KEYVALUE.vhd" 24 -1 0 } } { "KEYVALUE.vhd" "" { Text "E:/vhdl code/HD7279/KEYVALUE.vhd" 24 -1 0 } } { "KEYVALUE.vhd" "" { Text "E:/vhdl code/HD7279/KEYVALUE.vhd" 24 -1 0 } } { "KEYVALUE.vhd" "" { Text "E:/vhdl code/HD7279/KEYVALUE.vhd" 24 -1 0 } } { "KEYVALUE.vhd" "" { Text "E:/vhdl code/HD7279/KEYVALUE.vhd" 24 -1 0 } } { "KEYVALUE.vhd" "" { Text "E:/vhdl code/HD7279/KEYVALUE.vhd" 24 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "270 " "Info: Implemented 270 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "2 " "Info: Implemented 2 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_BIDIRS" "1 " "Info: Implemented 1 bidirectional pins" {  } {  } 0 0 "Implemented %1!d! bidirectional pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "264 " "Info: Implemented 264 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 35 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 35 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat May 17 23:09:46 2008 " "Info: Processing ended: Sat May 17 23:09:46 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Info: Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}