top_7279.map.qmsg

AD0820小程序

{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "U7279:inst\|FPGA_7279:inst3\|cmd_tmp\[4\] High " "Info: Power-up level of register \"U7279:inst\|FPGA_7279:inst3\|cmd_tmp\[4\]\" is not specified -- using power-up level of High to minimize register" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "U7279:inst\|FPGA_7279:inst3\|cmd_tmp\[4\] data_in VCC " "Warning: Reduced register \"U7279:inst\|FPGA_7279:inst3\|cmd_tmp\[4\]\" with stuck data_in port to stuck value VCC" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "U7279:inst\|FPGA_7279:inst3\|cmd_tmp\[3\] data_in GND " "Warning: Reduced register \"U7279:inst\|FPGA_7279:inst3\|cmd_tmp\[3\]\" with stuck data_in port to stuck value GND" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "U7279:inst\|FPGA_7279:inst3\|cmd_tmp1\[6\] data_in GND " "Warning: Reduced register \"U7279:inst\|FPGA_7279:inst3\|cmd_tmp1\[6\]\" with stuck data_in port to stuck value GND" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 196 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "U7279:inst\|FPGA_7279:inst3\|cmd_tmp1\[5\] data_in GND " "Warning: Reduced register \"U7279:inst\|FPGA_7279:inst3\|cmd_tmp1\[5\]\" with stuck data_in port to stuck value GND" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 196 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "U7279:inst\|FPGA_7279:inst3\|cmd_tmp1\[4\] High " "Info: Power-up level of register \"U7279:inst\|FPGA_7279:inst3\|cmd_tmp1\[4\]\" is not specified -- using power-up level of High to minimize register" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 196 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "U7279:inst\|FPGA_7279:inst3\|cmd_tmp1\[4\] data_in VCC " "Warning: Reduced register \"U7279:inst\|FPGA_7279:inst3\|cmd_tmp1\[4\]\" with stuck data_in port to stuck value VCC" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 196 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "U7279:inst\|FPGA_7279:inst3\|cmd_tmp1\[3\] data_in GND " "Warning: Reduced register \"U7279:inst\|FPGA_7279:inst3\|cmd_tmp1\[3\]\" with stuck data_in port to stuck value GND" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 196 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "U7279:inst\|FPGA_7279:inst3\|data_7279\[1\]\[7\] data_in GND " "Warning: Reduced register \"U7279:inst\|FPGA_7279:inst3\|data_7279\[1\]\[7\]\" with stuck data_in port to stuck value GND" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 256 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "U7279:inst\|FPGA_7279:inst3\|data_7279\[2\]\[7\] data_in GND " "Warning: Reduced register \"U7279:inst\|FPGA_7279:inst3\|data_7279\[2\]\[7\]\" with stuck data_in port to stuck value GND" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 256 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "U7279:inst\|FPGA_7279:inst3\|data_7279\[3\]\[7\] data_in GND " "Warning: Reduced register \"U7279:inst\|FPGA_7279:inst3\|data_7279\[3\]\[7\]\" with stuck data_in port to stuck value GND" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 256 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "U7279:inst\|FPGA_7279:inst3\|data_7279\[4\]\[7\] data_in GND " "Warning: Reduced register \"U7279:inst\|FPGA_7279:inst3\|data_7279\[4\]\[7\]\" with stuck data_in port to stuck value GND" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 256 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "U7279:inst\|FPGA_7279:inst3\|data_7279\[5\]\[7\] data_in GND " "Warning: Reduced register \"U7279:inst\|FPGA_7279:inst3\|data_7279\[5\]\[7\]\" with stuck data_in port to stuck value GND" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 256 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "U7279:inst\|FPGA_7279:inst3\|data_7279\[6\]\[7\] data_in GND " "Warning: Reduced register \"U7279:inst\|FPGA_7279:inst3\|data_7279\[6\]\[7\]\" with stuck data_in port to stuck value GND" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 256 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "U7279:inst\|FPGA_7279:inst3\|data_7279\[7\]\[7\] data_in GND " "Warning: Reduced register \"U7279:inst\|FPGA_7279:inst3\|data_7279\[7\]\[7\]\" with stuck data_in port to stuck value GND" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 256 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "U7279:inst\|FPGA_7279:inst3\|data_7279\[0\]\[7\] data_in GND " "Warning: Reduced register \"U7279:inst\|FPGA_7279:inst3\|data_7279\[0\]\[7\]\" with stuck data_in port to stuck value GND" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 256 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "U7279:inst\|div:inst\|clk_tmp div:inst2\|clk_tmp " "Info: Duplicate register \"U7279:inst\|div:inst\|clk_tmp\" merged to single register \"div:inst2\|clk_tmp\"" {  } { { "DIV.vhd" "" { Text "E:/vhdl code/HD7279/DIV.vhd" 23 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "U7279:inst\|FPGA_7279:inst3\|data_tmp\[7\] data_in GND " "Warning: Reduced register \"U7279:inst\|FPGA_7279:inst3\|data_tmp\[7\]\" with stuck data_in port to stuck value GND" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "U7279:inst\|FPGA_7279:inst3\|data_tmp1\[7\] data_in GND " "Warning: Reduced register \"U7279:inst\|FPGA_7279:inst3\|data_tmp1\[7\]\" with stuck data_in port to stuck value GND" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 196 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "KEYVALUE:inst1\|Q\[20\] KEYVALUE:inst1\|Q\[31\] " "Info: Duplicate register \"KEYVALUE:inst1\|Q\[20\]\" merged to single register \"KEYVALUE:inst1\|Q\[31\]\"" {  } { { "KEYVALUE.vhd" "" { Text "E:/vhdl code/HD7279/KEYVALUE.vhd" 49 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "KEYVALUE:inst1\|Q\[17\] KEYVALUE:inst1\|Q\[31\] " "Info: Duplicate register \"KEYVALUE:inst1\|Q\[17\]\" merged to single register \"KEYVALUE:inst1\|Q\[31\]\"" {  } { { "KEYVALUE.vhd" "" { Text "E:/vhdl code/HD7279/KEYVALUE.vhd" 49 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "KEYVALUE:inst1\|Q\[13\] KEYVALUE:inst1\|Q\[31\] " "Info: Duplicate register \"KEYVALUE:inst1\|Q\[13\]\" merged to single register \"KEYVALUE:inst1\|Q\[31\]\"" {  } { { "KEYVALUE.vhd" "" { Text "E:/vhdl code/HD7279/KEYVALUE.vhd" 49 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "KEYVALUE:inst1\|Q\[29\] KEYVALUE:inst1\|Q\[31\] " "Info: Duplicate register \"KEYVALUE:inst1\|Q\[29\]\" merged to single register \"KEYVALUE:inst1\|Q\[31\]\"" {  } { { "KEYVALUE.vhd" "" { Text "E:/vhdl code/HD7279/KEYVALUE.vhd" 49 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "KEYVALUE:inst1\|Q\[12\] KEYVALUE:inst1\|Q\[31\] " "Info: Duplicate register \"KEYVALUE:inst1\|Q\[12\]\" merged to single register \"KEYVALUE:inst1\|Q\[31\]\"" {  } { { "KEYVALUE.vhd" "" { Text "E:/vhdl code/HD7279/KEYVALUE.vhd" 49 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "KEYVALUE:inst1\|Q\[10\] KEYVALUE:inst1\|Q\[31\] " "Info: Duplicate register \"KEYVALUE:inst1\|Q\[10\]\" merged to single register \"KEYVALUE:inst1\|Q\[31\]\"" {  } { { "KEYVALUE.vhd" "" { Text "E:/vhdl code/HD7279/KEYVALUE.vhd" 49 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "KEYVALUE:inst1\|Q\[7\] KEYVALUE:inst1\|Q\[31\] " "Info: Duplicate register \"KEYVALUE:inst1\|Q\[7\]\" merged to single register \"KEYVALUE:inst1\|Q\[31\]\"" {  } { { "KEYVALUE.vhd" "" { Text "E:/vhdl code/HD7279/KEYVALUE.vhd" 49 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "KEYVALUE:inst1\|Q\[24\] KEYVALUE:inst1\|Q\[30\] " "Info: Duplicate register \"KEYVALUE:inst1\|Q\[24\]\" merged to single register \"KEYVALUE:inst1\|Q\[30\]\"" {  } { { "KEYVALUE.vhd" "" { Text "E:/vhdl code/HD7279/KEYVALUE.vhd" 49 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "KEYVALUE:inst1\|Q\[18\] KEYVALUE:inst1\|Q\[30\] " "Info: Duplicate register \"KEYVALUE:inst1\|Q\[18\]\" merged to single register \"KEYVALUE:inst1\|Q\[30\]\"" {  } { { "KEYVALUE.vhd" "" { Text "E:/vhdl code/HD7279/KEYVALUE.vhd" 49 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "KEYVALUE:inst1\|Q\[4\] KEYVALUE:inst1\|Q\[30\] " "Info: Duplicate register \"KEYVALUE:inst1\|Q\[4\]\" merged to single register \"KEYVALUE:inst1\|Q\[30\]\"" {  } { { "KEYVALUE.vhd" "" { Text "E:/vhdl code/HD7279/KEYVALUE.vhd" 49 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "KEYVALUE:inst1\|Q\[0\] KEYVALUE:inst1\|Q\[30\] " "Info: Duplicate register \"KEYVALUE:inst1\|Q\[0\]\" merged to single register \"KEYVALUE:inst1\|Q\[30\]\"" {  } { { "KEYVALUE.vhd" "" { Text "E:/vhdl code/HD7279/KEYVALUE.vhd" 49 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "KEYVALUE:inst1\|Q\[15\] KEYVALUE:inst1\|Q\[30\] " "Info: Duplicate register \"KEYVALUE:inst1\|Q\[15\]\" merged to single register \"KEYVALUE:inst1\|Q\[30\]\"" {  } { { "KEYVALUE.vhd" "" { Text "E:/vhdl code/HD7279/KEYVALUE.vhd" 49 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "KEYVALUE:inst1\|Q\[25\] KEYVALUE:inst1\|Q\[30\] " "Info: Duplicate register \"KEYVALUE:inst1\|Q\[25\]\" merged to single register \"KEYVALUE:inst1\|Q\[30\]\"" {  } { { "KEYVALUE.vhd" "" { Text "E:/vhdl code/HD7279/KEYVALUE.vhd" 49 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "KEYVALUE:inst1\|Q\[8\] KEYVALUE:inst1\|Q\[30\] " "Info: Duplicate register \"KEYVALUE:inst1\|Q\[8\]\" merged to single register \"KEYVALUE:inst1\|Q\[30\]\"" {  } { { "KEYVALUE.vhd" "" { Text "E:/vhdl code/HD7279/KEYVALUE.vhd" 49 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "KEYVALUE:inst1\|Q\[14\] KEYVALUE:inst1\|Q\[30\] " "Info: Duplicate register \"KEYVALUE:inst1\|Q\[14\]\" merged to single register \"KEYVALUE:inst1\|Q\[30\]\"" {  } { { "KEYVALUE.vhd" "" { Text "E:/vhdl code/HD7279/KEYVALUE.vhd" 49 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "KEYVALUE:inst1\|Q\[11\] KEYVALUE:inst1\|Q\[30\] " "Info: Duplicate register \"KEYVALUE:inst1\|Q\[11\]\" merged to single register \"KEYVALUE:inst1\|Q\[30\]\"" {  } { { "KEYVALUE.vhd" "" { Text "E:/vhdl code/HD7279/KEYVALUE.vhd" 49 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "KEYVALUE:inst1\|Q\[21\] KEYVALUE:inst1\|Q\[30\] " "Info: Duplicate register \"KEYVALUE:inst1\|Q\[21\]\" merged to single register \"KEYVALUE:inst1\|Q\[30\]\"" {  } { { "KEYVALUE.vhd" "" { Text "E:/vhdl code/HD7279/KEYVALUE.vhd" 49 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "KEYVALUE:inst1\|Q\[3\] KEYVALUE:inst1\|Q\[30\] " "Info: Duplicate register \"KEYVALUE:inst1\|Q\[3\]\" merged to single register \"KEYVALUE:inst1\|Q\[30\]\"" {  } { { "KEYVALUE.vhd" "" { Text "E:/vhdl code/HD7279/KEYVALUE.vhd" 49 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "KEYVALUE:inst1\|Q\[1\] KEYVALUE:inst1\|Q\[30\] " "Info: Duplicate register \"KEYVALUE:inst1\|Q\[1\]\" merged to single register \"KEYVALUE:inst1\|Q\[30\]\"" {  } { { "KEYVALUE.vhd" "" { Text "E:/vhdl code/HD7279/KEYVALUE.vhd" 49 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "KEYVALUE:inst1\|Q\[9\] KEYVALUE:inst1\|Q\[30\] " "Info: Duplicate register \"KEYVALUE:inst1\|Q\[9\]\" merged to single register \"KEYVALUE:inst1\|Q\[30\]\"" {  } { { "KEYVALUE.vhd" "" { Text "E:/vhdl code/HD7279/KEYVALUE.vhd" 49 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "KEYVALUE:inst1\|Q\[26\] KEYVALUE:inst1\|Q\[30\] " "Info: Duplicate register \"KEYVALUE:inst1\|Q\[26\]\" merged to single register \"KEYVALUE:inst1\|Q\[30\]\"" {  } { { "KEYVALUE.vhd" "" { Text "E:/vhdl code/HD7279/KEYVALUE.vhd" 49 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "KEYVALUE:inst1\|Q\[23\] KEYVALUE:inst1\|Q\[30\] " "Info: Duplicate register \"KEYVALUE:inst1\|Q\[23\]\" merged to single register \"KEYVALUE:inst1\|Q\[30\]\"" {  } { { "KEYVALUE.vhd" "" { Text "E:/vhdl code/HD7279/KEYVALUE.vhd" 49 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "KEYVALUE:inst1\|Q\[5\] KEYVALUE:inst1\|Q\[30\] " "Info: Duplicate register \"KEYVALUE:inst1\|Q\[5\]\" merged to single register \"KEYVALUE:inst1\|Q\[30\]\"" {  } { { "KEYVALUE.vhd" "" { Text "E:/vhdl code/HD7279/KEYVALUE.vhd" 49 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "KEYVALUE:inst1\|Q\[27\] KEYVALUE:inst1\|Q\[30\] " "Info: Duplicate register \"KEYVALUE:inst1\|Q\[27\]\" merged to single register \"KEYVALUE:inst1\|Q\[30\]\"" {  } { { "KEYVALUE.vhd" "" { Text "E:/vhdl code/HD7279/KEYVALUE.vhd" 49 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "KEYVALUE:inst1\|Q\[22\] KEYVALUE:inst1\|Q\[30\] " "Info: Duplicate register \"KEYVALUE:inst1\|Q\[22\]\" merged to single register \"KEYVALUE:inst1\|Q\[30\]\"" {  } { { "KEYVALUE.vhd" "" { Text "E:/vhdl code/HD7279/KEYVALUE.vhd" 49 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "KEYVALUE:inst1\|Q\[6\] KEYVALUE:inst1\|Q\[30\] " "Info: Duplicate register \"KEYVALUE:inst1\|Q\[6\]\" merged to single register \"KEYVALUE:inst1\|Q\[30\]\"" {  } { { "KEYVALUE.vhd" "" { Text "E:/vhdl code/HD7279/KEYVALUE.vhd" 49 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "KEYVALUE:inst1\|Q\[16\] KEYVALUE:inst1\|Q\[28\] " "Info: Duplicate register \"KEYVALUE:inst1\|Q\[16\]\" merged to single register \"KEYVALUE:inst1\|Q\[28\]\"" {  } { { "KEYVALUE.vhd" "" { Text "E:/vhdl code/HD7279/KEYVALUE.vhd" 49 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "KEYVALUE:inst1\|Q\[19\] KEYVALUE:inst1\|Q\[28\] " "Info: Duplicate register \"KEYVALUE:inst1\|Q\[19\]\" merged to single register \"KEYVALUE:inst1\|Q\[28\]\"" {  } { { "KEYVALUE.vhd" "" { Text "E:/vhdl code/HD7279/KEYVALUE.vhd" 49 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}