top_7279.map.qmsg

AD0820小程序

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Display8 U7279:inst\|Display8:inst5 " "Info: Elaborating entity \"Display8\" for hierarchy \"U7279:inst\|Display8:inst5\"" {  } { { "U7279.bdf" "inst5" { Schematic "E:/vhdl code/HD7279/U7279.bdf" { { 368 256 424 464 "inst5" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Din Display8.vhd(27) " "Warning (10492): VHDL Process Statement warning at Display8.vhd(27): signal \"Din\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "Display8.vhd" "" { Text "E:/vhdl code/HD7279/Display8.vhd" 27 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Din Display8.vhd(28) " "Warning (10492): VHDL Process Statement warning at Display8.vhd(28): signal \"Din\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "Display8.vhd" "" { Text "E:/vhdl code/HD7279/Display8.vhd" 28 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Din Display8.vhd(29) " "Warning (10492): VHDL Process Statement warning at Display8.vhd(29): signal \"Din\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "Display8.vhd" "" { Text "E:/vhdl code/HD7279/Display8.vhd" 29 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Din Display8.vhd(30) " "Warning (10492): VHDL Process Statement warning at Display8.vhd(30): signal \"Din\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "Display8.vhd" "" { Text "E:/vhdl code/HD7279/Display8.vhd" 30 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Din Display8.vhd(31) " "Warning (10492): VHDL Process Statement warning at Display8.vhd(31): signal \"Din\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "Display8.vhd" "" { Text "E:/vhdl code/HD7279/Display8.vhd" 31 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Din Display8.vhd(32) " "Warning (10492): VHDL Process Statement warning at Display8.vhd(32): signal \"Din\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "Display8.vhd" "" { Text "E:/vhdl code/HD7279/Display8.vhd" 32 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Din Display8.vhd(33) " "Warning (10492): VHDL Process Statement warning at Display8.vhd(33): signal \"Din\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "Display8.vhd" "" { Text "E:/vhdl code/HD7279/Display8.vhd" 33 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Din Display8.vhd(34) " "Warning (10492): VHDL Process Statement warning at Display8.vhd(34): signal \"Din\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "Display8.vhd" "" { Text "E:/vhdl code/HD7279/Display8.vhd" 34 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "Display8.vhd(35) " "Info (10425): VHDL Case Statement information at Display8.vhd(35): OTHERS choice is never selected" {  } { { "Display8.vhd" "" { Text "E:/vhdl code/HD7279/Display8.vhd" 35 0 0 } }  } 0 10425 "VHDL Case Statement information at %1!s!: OTHERS choice is never selected" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "div U7279:inst\|div:inst " "Info: Elaborating entity \"div\" for hierarchy \"U7279:inst\|div:inst\"" {  } { { "U7279.bdf" "inst" { Schematic "E:/vhdl code/HD7279/U7279.bdf" { { 256 288 384 336 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "div U7279:inst\|div:inst1 " "Info: Elaborating entity \"div\" for hierarchy \"U7279:inst\|div:inst1\"" {  } { { "U7279.bdf" "inst1" { Schematic "E:/vhdl code/HD7279/U7279.bdf" { { 152 528 624 232 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "KEYVALUE KEYVALUE:inst1 " "Info: Elaborating entity \"KEYVALUE\" for hierarchy \"KEYVALUE:inst1\"" {  } { { "top.bdf" "inst1" { Schematic "E:/vhdl code/HD7279/top.bdf" { { 144 448 608 272 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "KEYVALUE.vhd(41) " "Info (10425): VHDL Case Statement information at KEYVALUE.vhd(41): OTHERS choice is never selected" {  } { { "KEYVALUE.vhd" "" { Text "E:/vhdl code/HD7279/KEYVALUE.vhd" 41 0 0 } }  } 0 10425 "VHDL Case Statement information at %1!s!: OTHERS choice is never selected" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "U7279:inst\|Display8:inst5\|D_BUS\[7\] data_in GND " "Warning: Reduced register \"U7279:inst\|Display8:inst5\|D_BUS\[7\]\" with stuck data_in port to stuck value GND" {  } { { "Display8.vhd" "" { Text "E:/vhdl code/HD7279/Display8.vhd" 42 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "U7279:inst\|Display8:inst5\|D_BUS\[6\] data_in GND " "Warning: Reduced register \"U7279:inst\|Display8:inst5\|D_BUS\[6\]\" with stuck data_in port to stuck value GND" {  } { { "Display8.vhd" "" { Text "E:/vhdl code/HD7279/Display8.vhd" 42 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "U7279:inst\|Display8:inst5\|D_BUS\[5\] data_in GND " "Warning: Reduced register \"U7279:inst\|Display8:inst5\|D_BUS\[5\]\" with stuck data_in port to stuck value GND" {  } { { "Display8.vhd" "" { Text "E:/vhdl code/HD7279/Display8.vhd" 42 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "U7279:inst\|Display8:inst5\|D_BUS\[4\] data_in GND " "Warning: Reduced register \"U7279:inst\|Display8:inst5\|D_BUS\[4\]\" with stuck data_in port to stuck value GND" {  } { { "Display8.vhd" "" { Text "E:/vhdl code/HD7279/Display8.vhd" 42 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "U7279:inst\|FPGA_7279:inst3\|cmd_tmp\[6\] data_in GND " "Warning: Reduced register \"U7279:inst\|FPGA_7279:inst3\|cmd_tmp\[6\]\" with stuck data_in port to stuck value GND" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "U7279:inst\|FPGA_7279:inst3\|cmd_tmp\[5\] data_in GND " "Warning: Reduced register \"U7279:inst\|FPGA_7279:inst3\|cmd_tmp\[5\]\" with stuck data_in port to stuck value GND" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 84 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}