top_7279.map.qmsg

AD0820小程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat May 17 23:09:37 2008 " "Info: Processing started: Sat May 17 23:09:37 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off top_7279 -c top_7279 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off top_7279 -c top_7279" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Display8.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file Display8.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Display8-one " "Info: Found design unit 1: Display8-one" {  } { { "Display8.vhd" "" { Text "E:/vhdl code/HD7279/Display8.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 Display8 " "Info: Found entity 1: Display8" {  } { { "Display8.vhd" "" { Text "E:/vhdl code/HD7279/Display8.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DIV.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file DIV.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 div-behav " "Info: Found design unit 1: div-behav" {  } { { "DIV.vhd" "" { Text "E:/vhdl code/HD7279/DIV.vhd" 16 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 div " "Info: Found entity 1: div" {  } { { "DIV.vhd" "" { Text "E:/vhdl code/HD7279/DIV.vhd" 10 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "FPGA_7279.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file FPGA_7279.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 FPGA_7279-behav " "Info: Found design unit 1: FPGA_7279-behav" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 30 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 FPGA_7279 " "Info: Found entity 1: FPGA_7279" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 8 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "E:/vhdl code/HD7279/AA.vhd " "Warning: Can't analyze file -- file E:/vhdl code/HD7279/AA.vhd is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "KEYVALUE.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file KEYVALUE.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 KEYVALUE-a " "Info: Found design unit 1: KEYVALUE-a" {  } { { "KEYVALUE.vhd" "" { Text "E:/vhdl code/HD7279/KEYVALUE.vhd" 17 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 KEYVALUE " "Info: Found entity 1: KEYVALUE" {  } { { "KEYVALUE.vhd" "" { Text "E:/vhdl code/HD7279/KEYVALUE.vhd" 7 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "U7279.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file U7279.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 U7279 " "Info: Found entity 1: U7279" {  } { { "U7279.bdf" "" { Schematic "E:/vhdl code/HD7279/U7279.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "top.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file top.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 top " "Info: Found entity 1: top" {  } { { "top.bdf" "" { Schematic "E:/vhdl code/HD7279/top.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "top " "Info: Elaborating entity \"top\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "U7279 U7279:inst " "Info: Elaborating entity \"U7279\" for hierarchy \"U7279:inst\"" {  } { { "top.bdf" "inst" { Schematic "E:/vhdl code/HD7279/top.bdf" { { 80 648 856 208 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "FPGA_7279 U7279:inst\|FPGA_7279:inst3 " "Info: Elaborating entity \"FPGA_7279\" for hierarchy \"U7279:inst\|FPGA_7279:inst3\"" {  } { { "U7279.bdf" "inst3" { Schematic "E:/vhdl code/HD7279/U7279.bdf" { { 304 520 704 480 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "cmd_7279 FPGA_7279.vhd(47) " "Info (10035): Verilog HDL or VHDL information at FPGA_7279.vhd(47): object \"cmd_7279\" declared but not used" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 47 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "f_edge_cnt FPGA_7279.vhd(59) " "Info (10035): Verilog HDL or VHDL information at FPGA_7279.vhd(59): object \"f_edge_cnt\" declared but not used" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 59 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "cmd_start_tmp FPGA_7279.vhd(64) " "Warning (10036): Verilog HDL or VHDL warning at FPGA_7279.vhd(64): object \"cmd_start_tmp\" assigned a value but never read" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 64 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "seg_r FPGA_7279.vhd(68) " "Info (10035): Verilog HDL or VHDL information at FPGA_7279.vhd(68): object \"seg_r\" declared but not used" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 68 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "FPGA_7279.vhd(188) " "Info (10425): VHDL Case Statement information at FPGA_7279.vhd(188): OTHERS choice is never selected" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 188 0 0 } }  } 0 10425 "VHDL Case Statement information at %1!s!: OTHERS choice is never selected" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "RD_N FPGA_7279.vhd(226) " "Warning (10492): VHDL Process Statement warning at FPGA_7279.vhd(226): signal \"RD_N\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 226 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "FPGA_7279.vhd(276) " "Info (10425): VHDL Case Statement information at FPGA_7279.vhd(276): OTHERS choice is never selected" {  } { { "FPGA_7279.vhd" "" { Text "E:/vhdl code/HD7279/FPGA_7279.vhd" 276 0 0 } }  } 0 10425 "VHDL Case Statement information at %1!s!: OTHERS choice is never selected" 0 0}